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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PM7346 S/UNITM
QJET
S/UNI-QJET
SATURN QUAD USER NETWORK INTERFACE FOR J2/E3/T3
DATASHEET
PROPRIETARY AND CONFIDENTIAL ISSUE 6: MAY 1999
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REVISION HISTORY Issue No. 6 Issue Date May 14, 1999 Details of Change * The S/UNI-QJET requires a software initialization sequence in order to guarantee proper device operation and long term reliability. Please refer to Section 12.1 of this document for the details on how to program this sequence. Updated the RFCLK and TFCLK pin descriptions to reflect that these pins are not 5V tolerant. Both pins are 3.3V only input pins. Documentation clarifications.
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PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
CONTENTS 1 2 3 4 5 6 7 8 9 FEATURES ............................................................................................... 1 APPLICATIONS ........................................................................................ 6 REFERENCES ......................................................................................... 7 APPLICATION EXAMPLES .................................................................... 10 BLOCK DIAGRAM.................................................................................. 13 DESCRIPTION ....................................................................................... 17 PIN DIAGRAM ........................................................................................ 21 PIN DESCRIPTION ................................................................................ 22 FUNCTIONAL DESCRIPTION ............................................................... 59 9.1 9.2 9.3 DS3 FRAMER.............................................................................. 59 E3 FRAMER ................................................................................ 61 J2 FRAMER ................................................................................. 63 9.3.1 J2 FRAME FIND ALGORITHMS....................................... 65 9.4 9.5 9.6 9.7 9.8 9.9 9.10 9.11 PMON PERFORMANCE MONITOR ACCUMULATOR................ 68 RBOC BIT-ORIENTED CODE DETECTOR ................................. 68 RDLC FACILITY DATA LINK RECEIVER..................................... 69 SPLR PLCP LAYER RECEIVER ................................................. 70 ATMF ATM CELL DELINEATOR .................................................. 70 RXCP-50 RECEIVE CELL PROCESSOR ................................... 72 RXFF RECEIVE FIFO.................................................................. 74 CPPM CELL AND PLCP PERFORMANCE MONITOR ............... 75
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE i
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
9.12 9.13 9.14 9.15 9.16 9.17 9.18 9.19 9.20 9.21 9.22 9.23 10 11
PRGD PSEUDO-RANDOM SEQUENCE GENERATOR/DETECTOR .......................................................... 75 DS3 TRANSMITTER.................................................................... 76 E3 TRANSMITTER ...................................................................... 77 J2 TRANSMITTER....................................................................... 78 XBOC BIT ORIENTED CODE GENERATOR .............................. 79 TDPR FACILITY DATA LINK TRANSMITTER .............................. 79 SPLT SMDS PLCP LAYER TRANSMITTER ................................ 81 TXCP-50 TRANSMIT CELL PROCESSOR ................................. 82 TXFF TRANSMIT FIFO................................................................ 83 TTB TRAIL TRACE BUFFER ....................................................... 83 JTAG TEST ACCESS PORT ........................................................ 84 MICROPROCESSOR INTERFACE ............................................. 84
NORMAL MODE REGISTER DESCRIPTION........................................ 91 TEST FEATURES DESCRIPTION ....................................................... 294 11.1 11.2 TEST MODE 0 DETAILS ........................................................... 300 JTAG TEST PORT...................................................................... 305
12
OPERATION ......................................................................................... 308 12.1 12.2 12.3 SOFTWARE INITIALIZATION SEQUENCE ............................... 308 REGISTER SETTINGS FOR BASIC CONFIGURATIONS ........ 310 PLCP FRAME FORMATS .......................................................... 311 12.3.1 PLCP PATH OVERHEAD OCTET PROCESSING .......... 314 12.4 12.5 DS3 FRAME FORMAT .............................................................. 319 G.751 E3 FRAME FORMAT....................................................... 321
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
12.6 12.7 12.8 12.9
G.832 E3 FRAME FORMAT....................................................... 323 J2 FRAME FORMAT .................................................................. 325 S/UNI-QJET CELL DATA STRUCTURE..................................... 327 RESETTING THE RXFF AND TXFF FIFOS .............................. 331
12.10 SERVICING INTERRUPTS........................................................ 331 12.11 USING THE PERFORMANCE MONITORING FEATURES ....... 332 12.12 USING THE INTERNAL FDL TRANSMITTER ........................... 333 12.13 USING THE INTERNAL DATA LINK RECEIVER ....................... 336 12.14 PRGD PATTERN GENERATION................................................ 341 12.14.1 GENERATING AND DETECTING REPETITIVE PATTERNS ...................................................................... 341 12.14.2 COMMON TEST PATTERNS ...........................................
........................................................................................ 342 12.15 JTAG SUPPORT ........................................................................ 344 13 14 15 16 17 18 19 FUNCTIONAL TIMING ......................................................................... 353 ABSOLUTE MAXIMUM RATINGS........................................................ 380 D.C. CHARACTERISTICS .................................................................... 381 MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS ...... 384 A.C. TIMING CHARACTERISTICS ....................................................... 388 ORDERING AND THERMAL INFORMATION ...................................... 405 MECHANICAL INFORMATION............................................................. 406
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LIST OF REGISTERS REGISTER 000H, 100H, 200H, 300H: S/UNI-QJET CONFIGURATION 1....... 92 REGISTER 001H, 101H, 201H, 301H: S/UNI-QJET CONFIGURATION 2....... 95 REGISTER 002H, 102H, 202H, 302H: S/UNI-QJET TRANSMIT CONFIGURATION .................................................................................. 97 REGISTER 003H, 103H, 203H, 303H: S/UNI-QJET RECEIVE CONFIGURATION ................................................................................ 100 REGISTER 004H, 104H, 204H, 304H: S/UNI-QJET DATA LINK AND FERF/RAI CONTROL ............................................................................................ 103 REGISTER 005H, 105H, 205H, 305H: S/UNI-QJET INTERRUPT STATUS... 107 REGISTER 006H: S/UNI-QJET IDENTIFICATION, MASTER RESET, AND GLOBAL MONITOR UPDATE............................................................... 108 REGISTER 007H, 107H, 207H, 307H: S/UNI-QJET CLOCK ACTIVITY MONITOR AND INTERRUPT IDENTIFICATION .................................. 110 REGISTER 008H, 108H, 208H, 308H: SPLR CONFIGURATION .................. 112 REGISTER 009H, 109H, 209H, 309H: SPLR INTERRUPT ENABLE ............ 114 REGISTER 00AH, 10AH, 20AH, 30AH: SPLR INTERRUPT STATUS............ 116 REGISTER 00BH, 10BH, 20BH, 30BH: SPLR STATUS................................. 118 REGISTER 00CH, 10CH, 20CH, 30CH: SPLT CONFIGURATION................. 120 REGISTER 00DH, 10DH, 20DH, 30DH: SPLT CONTROL............................. 123 REGISTER 00EH, 10EH, 20EH, 30EH: SPLT DIAGNOSTICS AND G1 OCTET .............................................................................................................. 125 REGISTER 00FH, 10FH, 20FH, 30FH: SPLT F1 OCTET .............................. 127 REGISTER 010H, 110H, 210H, 310H: CHANGE OF PMON PERFORMANCE METERS............................................................................................... 128
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 011H, 111H, 211H, 311H: PMON INTERRUPT ENABLE/STATUS .............................................................................................................. 130 REGISTER 014H, 114H, 214H, 314H: PMON LINE CODE VIOLATION EVENT COUNT LSB ......................................................................................... 131 REGISTER 015H, 115H, 215H, 315H: PMON LINE CODE VIOLATION EVENT COUNT MSB ........................................................................................ 132 REGISTER 016H, 116H, 216H, 316H: PMON FRAMING BIT ERROR EVENT COUNT LSB ......................................................................................... 133 REGISTER 017H, 117H, 217H, 317H: PMON FRAMING BIT ERROR EVENT COUNT MSB ........................................................................................ 134 REGISTER 018H, 118H, 218H, 318H: PMON EXCESSIVE ZERO COUNT LSB .............................................................................................................. 135 REGISTER 019H, 119H, 219H, 319H: PMON EXCESSIVE ZERO COUNT MSB .............................................................................................................. 136 REGISTER 01AH, 11AH, 21AH, 31AH: PMON PARITY ERROR EVENT COUNT LSB....................................................................................................... 137 REGISTER 01BH, 11BH, 21BH, 31BH: PMON PARITY ERROR EVENT COUNT MSB...................................................................................................... 138 REGISTER 01CH, 11CH, 21CH, 31CH: PMON PATH PARITY ERROR EVENT COUNT LSB ......................................................................................... 139 REGISTER 01DH, 11DH, 21DH, 31DH: PMON PATH PARITY ERROR EVENT COUNT MSB ........................................................................................ 140 REGISTER 01EH, 11EH, 21EH, 31EH: PMON FEBE/J2-EXZS EVENT COUNT LSB....................................................................................................... 141 REGISTER 01FH, 11FH, 21FH, 31FH: PMON FEBE/J2-EXZS EVENT COUNT MSB...................................................................................................... 142 REGISTER 021H, 121H, 221H, 321H: CPPM CHANGE OF CPPM PERFORMANCE METERS.................................................................. 144 REGISTER 022H, 122H, 222H, 322H: CPPM B1 ERROR COUNT LSB ....... 145
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 023H, 123H, 223H, 323H: CPPM B1 ERROR COUNT MSB ...... 146 REGISTER 024H, 124H, 224H, 324H: CPPM FRAMING ERROR EVENT COUNT LSB ......................................................................................... 147 REGISTER 025H, 125H, 225H, 325H: CPPM FRAMING ERROR EVENT COUNT MSB ........................................................................................ 148 REGISTER 026H, 126H, 226H, 326H: CPPM FEBE COUNT LSB................ 149 REGISTER 027H, 127H, 227H, 327H: CPPM FEBE COUNT MSB............... 150 REGISTER 030H, 130H, 230H, 330H: DS3 FRMR CONFIGURATION ......... 151 REGISTER 031H, 131H, 231H, 331H: DS3 FRMR INTERRUPT ENABLE (ACE=0)................................................................................................ 153 REGISTER 031H, 131H, 231H, 331H: DS3 FRMR ADDITIONAL CONFIGURATION REGISTER (ACE=1) .............................................. 155 REGISTER 032H, 132H, 232H, 332H: DS3 FRMR INTERRUPT STATUS .... 158 REGISTER 033H, 133H, 233H, 333H: DS3 FRMR STATUS.......................... 160 REGISTER 034H, 134H, 234H, 334H: DS3 TRAN CONFIGURATION .......... 162 REGISTER 035H, 135H, 235H, 335H: DS3 TRAN DIAGNOSTIC ................. 164 REGISTER 038H, 138H, 238H, 338H: E3 FRMR FRAMING OPTIONS........ 166 REGISTER 039H, 139H, 239H, 339H: E3 FRMR MAINTENANCE OPTIONS .............................................................................................................. 168 REGISTER 03AH, 13AH, 23AH, 33AH: E3 FRMR FRAMING INTERRUPT ENABLE ............................................................................................... 170 REGISTER 03BH, 13BH, 23BH, 33BH: E3 FRMR FRAMING INTERRUPT INDICATION AND STATUS................................................................... 172 REGISTER 03CH, 13CH, 23CH, 33CH: E3 FRMR MAINTENANCE EVENT INTERRUPT ENABLE .......................................................................... 175 REGISTER 03DH, 13DH, 23DH, 33DH: E3 FRMR MAINTENANCE EVENT INTERRUPT INDICATION .................................................................... 177
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 03EH, 13EH, 23EH, 33EH: E3 FRMR MAINTENANCE EVENT STATUS ................................................................................................ 179 REGISTER 040H, 140H, 240H, 340H: E3 TRAN FRAMING OPTIONS ........ 181 REGISTER 041H, 141H, 241H, 341H: E3 TRAN STATUS AND DIAGNOSTIC OPTIONS ............................................................................................. 184 REGISTER 042H, 142H, 242H, 342H: E3 TRAN BIP-8 ERROR MASK ........ 186 REGISTER 043H, 143H, 243H, 343H: E3 TRAN MAINTENANCE AND ADAPTATION OPTIONS....................................................................... 187 REGISTER 044H, 144H, 244H, 344H: J2-FRMR CONFIGURATION ............ 189 REGISTER 045H, 145H, 245H, 345H: J2-FRMR STATUS............................. 191 REGISTER 046H, 146H, 246H, 346H: J2-FRMR ALARM INTERRUPT ENABLE .............................................................................................................. 192 REGISTER 047H, 147H, 247H, 347H: J2-FRMR ALARM INTERRUPT STATUS .............................................................................................................. 194 REGISTER 048H, 148H, 248H, 348H: J2-FRMR ERROR/XBIT INTERRUPT ENABLE ............................................................................................... 196 REGISTER 049H, 149H, 249H, 349H: J2-FRMR ERROR/XBIT INTERRUPT STATUS ................................................................................................ 198 REGISTER 04CH, 14CH, 24CH, 34CH: J2-TRAN CONFIGURATION .......... 200 REGISTER 04DH, 14DH, 24DH, 34DH: J2-TRAN DIAGNOSTIC.................. 202 REGISTER 04EH, 14EH, 24EH, 34EH: J2-TRAN TS97 SIGNALING............ 204 REGISTER 04FH, 14FH, 24FH, 34FH: J2-TRAN TS98 SIGNALING............. 205 REGISTER 050H, 150H, 250H,350H: RDLC CONFIGURATION................... 206 REGISTER 051H, 151H, 251H, 351H: RDLC INTERRUPT CONTROL......... 208 REGISTER 052H, 152H, 252H, 352H: RDLC STATUS .................................. 209 REGISTER 053H, 153H, 253H, 353H: RDLC DATA....................................... 212
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 054H, 154H, 254H, 354H: RDLC PRIMARY ADDRESS MATCH...... .............................................................................................................. 213 REGISTER 055H, 155H, 255H, 355H: RDLC SECONDARY ADDRESS MATCH .............................................................................................................. 214 REGISTER 058H, 158H, 258H, 358H: TDPR CONFIGURATION .................. 215 REGISTER 059H, 159H, 259H, 359H: TDPR UPPER TRANSMIT THRESHOLD .............................................................................................................. 217 REGISTER 05AH, 15AH, 25AH, 35AH: TDPR LOWER INTERRUPT THRESHOLD ....................................................................................... 218 REGISTER 05BH, 15BH, 25BH, 35BH: TDPR INTERRUPT ENABLE .......... 219 REGISTER 05CH, 15CH, 25CH, 35CH: TDPR INTERRUPT STATUS/UDR CLEAR.................................................................................................. 221 REGISTER 05DH, 15DH, 25DH, 35DH: TDPR TRANSMIT DATA.................. 223 REGISTER 060H, 160H, 260H, 360H: RXCP-50 CONFIGURATION 1 ......... 224 REGISTER 061H, 161H, 261H, 361H: RXCP-50 CONFIGURATION 2 ......... 226 REGISTER 062H, 162H, 262H, 362H: RXCP-50 FIFO/UTOPIA CONTROL & CONFIG................................................................................................ 229 REGISTER 063H, 163H, 263H, 363H: RXCP-50 INTERRUPT ENABLES AND COUNTER STATUS.............................................................................. 231 REGISTER 064H, 164H, 264H, 364H: RXCP-50 STATUS/INTERRUPT STATUS .............................................................................................................. 233 REGISTER 065H, 165H, 265H, 365H: RXCP-50 LCD COUNT THRESHOLD (MSB) ................................................................................................... 235 REGISTER 066H, 166H, 266H, 366H: RXCP-50 LCD COUNT THRESHOLD (LSB) .................................................................................................... 236 REGISTER 067H, 167H, 267H, 367H: RXCP-50 IDLE CELL HEADER PATTERN.............................................................................................. 238
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 068H, 168H, 268H, 368H: RXCP-50 IDLE CELL HEADER MASK .............................................................................................................. 239 REGISTER 069H, 169H, 269H, 369H: RXCP-50 CORRECTED HCS ERROR COUNT................................................................................................. 240 REGISTER 06AH, 16AH, 26AH, 36AH: RXCP-50 UNCORRECTED HCS ERROR COUNT ................................................................................... 241 REGISTER 06BH, 16BH, 26BH, 36BH: RXCP-50 RECEIVE CELL COUNTER (LSB) .................................................................................................... 242 REGISTER 06CH, 16CH, 26CH, 36CH: RXCP-50 RECEIVE CELL COUNTER .............................................................................................................. 243 REGISTER 06DH, 16DH, 26DH, 36DH: RXCP-50 RECEIVE CELL COUNTER (MSB) ................................................................................................... 244 REGISTER 06EH, 16EH, 26EH, 36EH: RXCP-50 IDLE CELL COUNTER (LSB) .............................................................................................................. 245 REGISTER 06FH, 16FH, 26FH, 36FH: RXCP-50 IDLE CELL COUNTER .... 246 REGISTER 070H, 170H, 270H, 370H: RXCP-50 IDLE CELL COUNTER (MSB) .............................................................................................................. 247 REGISTER 080H, 180H, 280H, 380H: TXCP-50 CONFIGURATION 1 .......... 248 REGISTER 081H, 181H, 281H, 381H: TXCP-50 CONFIGURATION 2 .......... 251 REGISTER 082H, 182H, 282H, 382H: TXCP-50 CELL COUNT STATUS...... 253 REGISTER 083H, 183H, 283H, 383H: TXCP-50 INTERRUPT ENABLE/STATUS .............................................................................................................. 254 REGISTER 084H, 184H, 284H, 384H: TXCP-50 IDLE CELL HEADER CONTROL ............................................................................................ 256 REGISTER 085H, 185H, 285H, 385H: TXCP-50 IDLE CELL PAYLOAD CONTROL ............................................................................................ 257 REGISTER 086H, 186H, 286H, 386H: TXCP-50 TRANSMIT CELL COUNT (LSB) .................................................................................................... 258 REGISTER 087H, 187H, 287H, 387H: TXCP-50 TRANSMIT CELL COUNT. 259
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 088H, 188H, 288H, 388H: TXCP-50 TRANSMIT CELL COUNT (MSB) ................................................................................................... 260 REGISTER 090H, 190H, 290H, 390H: TTB CONTROL ................................. 261 REGISTER 091H, 191H, 291H, 391H: TTB TRAIL TRACE IDENTIFIER STATUS .............................................................................................................. 263 REGISTER 092H, 192H, 292H, 392H: TTB INDIRECT ADDRESS ............... 265 REGISTER 093H, 193H, 293H, 393H: TTB INDIRECT DATA ........................ 266 REGISTER 094H, 194H, 294H, 394H: TTB EXPECTED PAYLOAD TYPE LABEL267 REGISTER 095H, 195H, 295H, 395H: TTB PAYLOAD TYPE LABEL CONTROL/STATUS .............................................................................. 269 REGISTER 098H, 198H, 298H, 398H: RBOC CONFIGURATION/INTERRUPT ENABLE ............................................................................................... 271 REGISTER 099H, 199H, 299H, 399H: RBOC INTERRUPT STATUS ............ 272 REGISTER 09AH, 19AH, 29AH, 39AH: XBOC CODE................................... 273 REGISTER 09BH, 19BH, 29BH, 39BH: S/UNI-QJET MISC........................... 274 REGISTER 09CH, 19CH, 29CH, 39CH: S/UNI-QJET FRMR LOF STATUS. .. 277 REGISTER 0A0H, 1A0H, 2A0H, 3A0H: PRGD CONTROL............................ 279 REGISTER 0A1H, 1A1H, 2A1H, 3A1H: PRGD INTERRUPT ENABLE/STATUS .............................................................................................................. 281 REGISTER 0A2H, 1A2H, 2A2H, 3A2H: PRGD LENGTH .............................. 283 REGISTER 0A3H, 1A3H, 2A3H, 3A3H: PRGD TAP....................................... 284 REGISTER 0A4H, 1A4H, 2A4H, 3A4H: PRGD ERROR INSERTION REGISTER .............................................................................................................. 285 REGISTER 0A8H, 1A8H, 2A8H, 3A8H: PATTERN INSERTION #1 ............... 286 REGISTER 0A9H, 1A9H, 2A9H, 3A9H: PATTERN INSERTION #2 ............... 287
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
REGISTER 0AAH, 1AAH, 2AAH, 3AAH: PATTERN INSERTION #3.............. 288 REGISTER 0ABH, 1ABH, 2ABH, 3ABH: PATTERN INSERTION #4.............. 289 REGISTER 0ACH, 1ACH, 2ACH, 3ACH: PRGD PATTERN DETECTOR #1 .. 290 REGISTER 0ADH, 1ADH, 2ADH, 3ADH: PRGD PATTERN DETECTOR #2.. 291 REGISTER 0AEH, 1AEH, 2AEH, 3AEH: PRGD PATTERN DETECTOR #3 .. 292 REGISTER 0AFH, 1AFH, 2AFH, 3AFH: PRGD PATTERN DETECTOR #4 ... 293 REGISTER 400H: S/UNI-QJET MASTER TEST ............................................ 299
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LIST OF FIGURES FIGURE 1 - S/UNI-QJET, AS AN ATM PHY, IN AN ATM SWITCH................... 10 FIGURE 3 - S/UNI-QJET, AS A QUAD FRAMER DEVICE, IN FRAME RELAY EQUIPMENT ..................................................................................................... 11 FIGURE 5 - S/UNI-QJET, AS A CELL PROCESSOR, IN DSLAM EQUIPMENT 12 FIGURE 7 - NORMAL OPERATING MODE..................................................... 13 FIGURE 8 - DS3/E3/J2 FRAMERS BYPASSED.............................................. 14 FIGURE 9 - DS3/E3/J2 TRANSCEIVER MODE .............................................. 15 FIGURE 10- LOOPBACK MODES.................................................................... 16 FIGURE 11- FRAMING ALGORITHM (CRC_REFR = 0).................................. 66 FIGURE 13- FRAMING ALGORITHM (CRC_REFR = 1).................................. 67 FIGURE 15- CELL DELINEATION STATE DIAGRAM....................................... 71 FIGURE 17- HCS VERIFICATION STATE DIAGRAM ....................................... 74 FIGURE 19- DS3 PLCP FRAME FORMAT ..................................................... 312 FIGURE 13- DS1 PLCP FRAME FORMAT ..................................................... 313 FIGURE 14- G.751 E3 PLCP FRAME FORMAT............................................. 313 FIGURE 23- E1 PLCP FRAME FORMAT ....................................................... 314 FIGURE 16- DS3 FRAME STRUCTURE ........................................................ 319 FIGURE 18- G.751 E3 FRAME STRUCTURE................................................ 321 FIGURE 20- G.832 E3 FRAME STRUCTURE................................................ 323 FIGURE 22- J2 FRAME STRUCTURE ........................................................... 325 FIGURE 24- 16-BIT WIDE, 26 WORD STRUCTURE...................................... 327 FIGURE 26- 16-BIT WIDE, 27 WORD STRUCTURE...................................... 328
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIGURE 28- 8-BIT WIDE, 52 WORD STRUCTURE........................................ 329 FIGURE 30- 8-BIT WIDE, 53 WORD STRUCTURE........................................ 330 FIGURE 32- TYPICAL DATA FRAME.............................................................. 339 FIGURE 33- EXAMPLE MULTI-PACKET OPERATIONAL SEQUENCE ......... 340 FIGURE 34- PRGD PATTERN GENERATOR ................................................. 341 FIGURE 36- BOUNDARY SCAN ARCHITECTURE........................................ 345 FIGURE 37- TAP CONTROLLER FINITE STATE MACHINE .......................... 347 FIGURE 38- INPUT OBSERVATION CELL (IN_CELL) ................................... 350 FIGURE 39- OUTPUT CELL (OUT_CELL)..................................................... 351 FIGURE 40- BI-DIRECTIONAL CELL (IO_CELL)........................................... 351 FIGURE 41- LAYOUT OF OUTPUT ENABLE AND BI-DIRECTIONAL CELLS ..................................................................................................... 352 FIGURE 42- RECEIVE DS1 STREAM............................................................ 353 FIGURE 43- RECEIVE E1 STREAM .............................................................. 353 FIGURE 44- RECEIVE BIPOLAR DS3 STREAM ........................................... 354 FIGURE 45- RECEIVE UNIPOLAR DS3 STREAM ........................................ 354 FIGURE 46- RECEIVE BIPOLAR E3 STREAM.............................................. 355 FIGURE 47- RECEIVE UNIPOLAR E3 STREAM ........................................... 355 FIGURE 48- RECEIVE BIPOLAR J2 STREAM .............................................. 356 FIGURE 49- RECEIVE UNIPOLAR J2 STREAM............................................ 356 FIGURE 50- GENERIC RECEIVE STREAM .................................................. 357 FIGURE 51- RECEIVE DS3 OVERHEAD....................................................... 357 FIGURE 52- RECEIVE G.832 E3 OVERHEAD............................................... 358
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIGURE 53- RECEIVE G.751 E3 OVERHEAD............................................... 359 FIGURE 54- RECEIVE J2 OVERHEAD .......................................................... 359 FIGURE 55- RECEIVE PLCP OVERHEAD .................................................... 360 FIGURE 56- TRANSMIT DS1 STREAM ......................................................... 361 FIGURE 57- TRANSMIT E1 STREAM ............................................................ 361 FIGURE 58- TRANSMIT BIPOLAR DS3 STREAM......................................... 362 FIGURE 59- TRANSMIT UNIPOLAR DS3 STREAM ...................................... 362 FIGURE 60- TRANSMIT BIPOLAR E3 STREAM ........................................... 363 FIGURE 61- TRANSMIT UNIPOLAR E3 STREAM......................................... 363 FIGURE 62- TRANSMIT BIPOLAR J2 STREAM ............................................ 364 FIGURE 63- TRANSMIT UNIPOLAR J2 STREAM ......................................... 364 FIGURE 64- GENERIC TRANSMIT STREAM................................................ 365 FIGURE 65- TRANSMIT DS3 OVERHEAD .................................................... 366 FIGURE 66- TRANSMIT G.832 E3 OVERHEAD ............................................ 367 FIGURE 67- TRANSMIT G.751 E3 OVERHEAD ............................................ 368 FIGURE 68- TRANSMIT J2 OVERHEAD........................................................ 368 FIGURE 69- TRANSMIT PLCP OVERHEAD .................................................. 369 FIGURE 70- FRAMER MODE DS3 TRANSMIT INPUT STREAM .................. 370 FIGURE 71- FRAMER MODE DS3 TRANSMIT INPUT STREAM WITH TGAPCLK ..................................................................................................... 370 FIGURE 72- FRAMER MODE DS3 RECEIVE OUTPUT STREAM ................ 371 FIGURE 73- FRAMER MODE DS3 RECEIVE OUTPUT STREAM WITH RGAPCLK ..................................................................................................... 371 FIGURE 74- FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM.......... 371
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xiv
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIGURE 75- FRAMER MODE G.751 E3 TRANSMIT INPUT STREAM WITH TGAPCLK ..................................................................................................... 372 FIGURE 76- FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM ........ 372 FIGURE 77- FRAMER MODE G.751 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK ..................................................................................................... 372 FIGURE 78- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM.......... 373 FIGURE 79- FRAMER MODE G.832 E3 TRANSMIT INPUT STREAM WITH TGAPCLK ..................................................................................................... 373 FIGURE 80- FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM ........ 374 FIGURE 81- FRAMER MODE G.832 E3 RECEIVE OUTPUT STREAM WITH RGAPCLK ..................................................................................................... 374 FIGURE 82- FRAMER MODE J2 TRANSMIT INPUT STREAM ..................... 374 FIGURE 83- FRAMER MODE J2 TRANSMIT INPUT STREAM WITH TGAPCLK ..................................................................................................... 375 FIGURE 84- FRAMER MODE J2 RECEIVE OUTPUT STREAM ................... 375 FIGURE 85- FRAMER MODE J2 RECEIVE OUTPUT STREAM WITH RGAPCLK ..................................................................................................... 375 FIGURE 86- MULTI-PHY POLLING AND ADDRESSING TRANSMIT CELL INTERFACE .................................................................................................... 376 FIGURE 87- MULTI-PHY POLLING AND ADDRESSING RECEIVE CELL INTERFACE .................................................................................................... 377 FIGURE 88- MICROPROCESSOR INTERFACE READ TIMING.................... 385 FIGURE 90- MICROPROCESSOR INTERFACE WRITE TIMING .................. 387 FIGURE 92- RSTB TIMING ............................................................................ 388 FIGURE 94- TRANSMIT ATM CELL INTERFACE TIMING............................. 389 FIGURE 96- RECEIVE ATM CELL INTERFACE TIMING ............................... 391 FIGURE 98- TRANSMIT INTERFACE TIMING ............................................... 394
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xv
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIGURE 100...................................................... - RECEIVE INTERFACE TIMING ..................................................................................................... 399 FIGURE 102.................................................. - JTAG PORT INTERFACE TIMING ..................................................................................................... 403
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xvi
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LIST OF TABLES TABLE 1 TABLE 2 TABLE 3 TABLE 4 TABLE 5 TABLE 6 TABLE 7 TABLE 8 TABLE 9 - SUPPORTED OPERATING FORMATS.......................................... 1 - REGISTER MEMORY MAP ......................................................... 84 - STATSEL[2:0] OPTIONS .............................................................. 96 - TFRM[1:0] TRANSMIT FRAME STRUCTURE CONFIGURATIONS ....................................................................................................... 98 - LOF[1:0] INTEGRATION PERIOD CONFIGURATION ............... 101 - RFRM[1:0] RECEIVE FRAME STRUCTURE CONFIGURATIONS ..................................................................................................... 101 - SPLR FORM[1:0] CONFIGURATIONS....................................... 113 - PLCP LOF DECLARATION/REMOVAL TIMES .......................... 118 - SPLT FORM[1:0] CONFIGURATIONS ....................................... 122
TABLE 10 - DS3 FRMR EXZS/LCV COUNT CONFIGURATIONS ................ 156 TABLE 11 - DS3 FRMR AIS CONFIGURATIONS ......................................... 157 TABLE 12 - E3 FRMR FORMAT[1:0] CONFIGURATIONS ............................ 167 TABLE 13 - E3 TRAN FORMAT[1:0] CONFIGURATIONS ............................. 181 TABLE 14 - J2 FRMR LOS THRESHOLD CONFIGURATIONS .................... 190 TABLE 15 - RDLC PBS[2:0] DATA STATUS ................................................... 210 TABLE 16 - RXCP-50 HCS FILTERING CONFIGURATIONS........................ 226 TABLE 17 - RXCP-50 CELL DELINATION ALGORITHM BASE ................... 227 TABLE 18 - RXCP-50 LCD INTEGRATION PERIODS .................................. 237 TABLE 19 - TXCP-50 FIFO DEPTH CONFIGURATIONS.............................. 252 TABLE 20 - TTB PAYLOAD TYPE MATCH CONFIGURATIONS.................... 267 TABLE 21 - PRGD PATTERN DETECTOR REGISTER CONFIGURATION .. 279
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xvii
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
TABLE 22 - PRGD GENERATED BIT ERROR RATE CONFIGURATIONS ... 285 TABLE 23 - TEST MODE REGISTER MEMORY MAP.................................. 294 TABLE 24 - TEST MODE 0 INPUT READ ADDRESS LOCATIONS.............. 300 TABLE 25 - TEST MODE 0 OUTPUT WRITE ADDRESS LOCATIONS ........ 302 TABLE 26 - INSTRUCTION REGISTER........................................................ 305 TABLE 27 - BOUNDARY SCAN REGISTER ................................................. 306 TABLE 28 - REGISTER SETTINGS FOR BASIC CONFIGURATIONS ......... 310 TABLE 29 - PLCP OVERHEAD PROCESSING ............................................ 314 TABLE 30 - PLCP PATH OVERHEAD IDENTIFIER CODES ......................... 317 TABLE 32 - DS3 PLCP TRAILER LENGTH .................................................. 318 TABLE 34 - E3 PLCP TRAILER LENGTH ..................................................... 318 TABLE 36 - DS3 FRAME OVERHEAD OPERATION .................................... 320 TABLE 37 - G.751 E3 FRAME OVERHEAD OPERATION ............................ 322 TABLE 38 - G.832 E3 FRAME OVERHEAD OPERATION ............................ 323 TABLE 39 - J2 FRAME OVERHEAD OPERATION........................................ 326 TABLE 40 - PSEUDO RANDOM PATTERN GENERATION (PS BIT = 0)...... 342 TABLE 41 - REPETITIVE PATTERN GENERATION (PS BIT = 1)................. 343 TABLE 42 - DS3 RECEIVE OVERHEAD BITS.............................................. 358 TABLE 43 - DS3 TRANSMIT OVERHEAD BITS ........................................... 366 TABLE 44 - ABSOLUTE MAXIMUM RATINGS.............................................. 380 TABLE 45 - DC CHARACTERISTICS............................................................ 381 TABLE 46 - MICROPROCESSOR INTERFACE READ ACCESS (FIGURE 88) ..................................................................................................... 384
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xviii
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
TABLE 47 - MICROPROCESSOR INTERFACE WRITE ACCESS (FIGURE 90) ..................................................................................................... 386 TABLE 48 - RSTB TIMING (FIGURE 92)....................................................... 388 TABLE 49 - TRANSMIT ATM CELL INTERFACE TIMING (FIGURE 94) ....... 388 TABLE 50 - RECEIVE ATM CELL INTERFACE TIMING (FIGURE 96) ......... 390 TABLE 51 - TRANSMIT INTERFACE TIMING (FIGURE 98) ......................... 392 TABLE 52 - RECEIVE INTERFACE TIMING (FIGURE 100).......................... 398 TABLE 53 - JTAG PORT INTERFACE (FIGURE 102) ................................... 402 TABLE 54 - PACKAGING INFORMATION ..................................................... 405 TABLE 55 - THERMAL INFORMATION ......................................................... 405
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE xix
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
1
FEATURES * Single chip quad ATM User Network Interface operating at 44.736 Mbit/s, 34.368 Mbit/s, and 6.312 Mbit/s conforming to ATMF-95-1207R1, ATMF-940406R5, and AF-PHY-0029.000. Each line can be individually configured for the desired rate. Implements ATM Direct Cell Mapping into DS1, DS3, E1, E3, and J2 transmission systems according to ITU-T Recommendation G.804. Provides a UTOPIA Level 2 compatible ATM-PHY Interface. Implements the Physical Layer Convergence Protocol (PLCP) for DS1 and DS3 transmission systems according to the ATM Forum User Network Interface Specification and ANSI TA-TSY-000773, TA-TSY-000772, and E1 and E3 transmission systems according to the ETSI 300-269 and ETSI 300270. Support is provided for SMDS and ATM mappings into various rate transmission systems as follows: - Supported Operating Formats Framer Only YES YES YES YES YES external external external external bypass SMDS PLCP Mapping YES YES YES n/a n/a YES YES YES YES n/a ATM Direct Mapping YES YES YES YES YES YES YES YES YES YES
* * *
*
Table 1
Rate
T3 (44.736 Mbit/s) E3 (34.368 Mbit/s) J2 (6.312 Mbit/s) E1 (2.048 Mbit/s) T1 (1.544 Mbit/s) Arbitrary Cell Rate (up to 52 Mbit/s)
Format
C-bit Parity M23 G.751 G.832 G.704 & NTT CRC-4 PCM30 ESF SF
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 1
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
* * * *
Implements the ATM physical layer for Broadband ISDN according to ITU-T Recommendation I.432. Provides on-chip DS3, E3 (G.751 and G.832), and J2 framers. Can be configured to be used solely as a DS3, E3, or J2 Framer. When configured to operate as a DS3, E3, or J2 Framer, gapped transmit and receive clocks can be optionally generated for interface to devices which only need access to payload data bits. Provides support for an arbitrary rate external transmission system interface up to a maximum rate of 52 Mbit/s which enables the S/UNI-QJET to be used as a quad ATM cell delineator. Uses the PMC-Sierra PM4341 T1XC, PM4344 TQUAD, PM6341 E1XC, and PM6344 EQUAD T1 and E1 framer/line interface chips for DS1 and E1 applications. Provides programmable pseudo-random test pattern generation, detection, and analysis features. Provides integral transmit and receive HDLC controllers with 128-byte FIFO depths. Provides performance monitoring counters suitable for accumulation periods of up to 1 second. Provides an 8-bit microprocessor interface for configuration, control and status monitoring. Provides a standard 5 signal P1149.1 JTAG test port for boundary scan board test purposes. Low power 3.3V CMOS technology with 5V tolerant inputs. Available in a high density 256-pin SBGA package (27mm x 27mm).
*
*
* * * * * * *
The receiver section: * Provides frame synchronization for the M23 or C-bit parity DS3 applications, alarm detection, and accumulates line code violations, framing errors, parity errors, path parity errors and FEBE events. In addition, far end alarm channel
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 2
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
codes are detected, and an integral HDLC receiver is provided to terminate the path maintenance data link. * Provides frame synchronization for the G.751 or G.832 E3 applications, alarm detection, and accumulates line code violations, framing errors, parity errors, and FEBE events. In addition, in G.832, the Trail Trace is detected, and an integral HDLC receiver is provided to terminate either the Network Requirement or the General Purpose data link. Provides frame synchronization for G.704 and NTT 6.312 Mbit/s J2 applications, alarm detection, and accumulates line code violations, framing errors, and CRC parity errors. An integral HDLC receiver is provided to terminate the data link. Provides frame synchronization, cell delineation and extraction for DS3, G.751 E3, G.832 E3, and G.704 and NTT J2 ATM direct-mapped formats. Provides PLCP frame synchronization, path overhead extraction, and cell extraction for DS1 PLCP DS3 PLCP E1 PLCP and G.751 E3 PLCP , , , formatted streams. Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the receive path with parity support, and multi-PHY (Level 2) control signals. Provides ATM framing using cell delineation. ATM cell delineation may optionally be disabled to allow passing of all cell bytes regardless of cell delineation status. Provides cell descrambling, header check sequence (HCS) error detection, idle cell filtering, header descrambling (for use with PPP packets), and accumulates the number of received idle cells, the number of received cells written to the FIFO, and the number of HCS errors. Provides a four cell FIFO for rate decoupling between the line, and a higher layer processing entity. FIFO latency may be reduced by changing the number of operational cell FIFOs. Provides a receive HDLC controller with a 128-byte FIFO to accumulate data link information. Provides detection of yellow alarm and loss of frame (LOF), and accumulates BIP-8 errors, framing errors and FEBE events.
*
* *
* *
*
*
* *
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 3
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
*
Provides programmable pseudo-random test-sequence detection (up to 2321 bit length patterns conforming to ITU-T O.151 standards) and analysis features.
The transmitter section: * Provides frame insertion for the M23 or C-bit parity DS3 applications, alarm insertion, and diagnostic features. In addition, far end alarm channel codes may be inserted, and an integral HDLC transmitter is provided to insert the path maintenance data link. Provides frame insertion for the G.751 or G.832 E3 applications, alarm insertion, and diagnostic features. In addition, for G.832, the Trail Trace is inserted, and an integral HDLC transmitter is provided to insert either the Network Requirement or the General Purpose data link. Provides frame insertion for G.704 6.312 Mbit/s J2 applications, alarm insertion, and diagnostic features. An integral HDLC transmitter is provided to insert the path maintenance data link. Provides frame insertion and path overhead insertion for DS1, DS3, E1 or E3 based PLCP formats. In addition, alarm insertion and diagnostic features are provided. Provides a 50 MHz 8-bit wide or 16-bit wide Utopia FIFO buffer in the transmit path with parity support and multi-PHY (Level 2) control signals. Provides optional ATM cell scrambling, header scrambling (for use with PPP packets), HCS generation/insertion, programmable idle cell insertion, diagnostics features and accumulates transmitted cells read from the FIFO. Provides a four cell FIFO for rate decoupling between the line and a higher layer processing entity. FIFO latency may be reduced by changing the number of operational cell FIFOs. Provides a transmit HDLC controller with a 128-byte FIFO. Provides an 8 kHz reference input for locking the transmit PLCP frame rate to an externally applied frame reference. Provides programmable pseudo-random test sequence generation (up to 232-1 bit length sequences conforming to ITU-T O.151 standards).
*
*
*
* *
*
* * *
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 4
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Diagnostic abilities include single bit error insertion or error insertion at bit error rates ranging from 10-1 to 10-7. Bypass and Loopback features: * Allows bypassing of the DS3, E3, and J2 framers to enable transmission system sublayer processing by an external device (for example, the PM4344 Quad DS1 Framer may be used for DS1-based services, and the PM6344 Quad E1 Framer may be used for E1-based services). Allows bypassing of the PLCP and ATM functions to enable use of the S/UNI-QJET as a quad DS3, E3, or J2 framer. Provides for diagnostic loopbacks, line loopbacks, and payload loopbacks.
* *
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
2
APPLICATIONS * * * * * * ATM or SMDS Switches, Multiplexers, and Routers SONET/SDH Mux E3/DS3 Tributary Interfaces PDH Mux J2/E3/DS3 Line Interfaces DS3/E3/J2 Digital Cross Connect Interfaces DS3/E3/J2 PPP Internet Access Interfaces DS3/E3/J2 Frame Relay Interfaces
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 6
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
3
REFERENCES
1. ANSI T1.627 - 1993, "Broadband ISDN - ATM Layer Functionality and Specification". 2. ANSI T1.107a - 1990, "Digital Hierarchy - Supplement to Formats Specifications (DS3 Format Applications)". 3. ANSI T1.107 - 1995, "Digital Hierarchy - Formats Specifications". 4. ANSI T1.646 - 1995, "Broadband ISDN - Physical Layer Specification for UserNetwork Interfaces Including DS1/ATM". 5. ATM Forum - ATM User-Network Interface Specification, V3.1, October, 1995. 6. ATM Forum - "UTOPIA, An ATM PHY Interface Specification, Level 2, Version 1", June, 1995. 7. ATM Forum, 94-0406R5, "E3 (34,368 kbps) Physical Layer Interface", Dec. 21, 1994. 8. ATM Forum, 95-1207R1, "DS3 Physical Layer Interface Specification", December 1995. 9. ATM Forum, af-phy-0029.000, "6,312 Kbps UNI Specification, Version 1.0", June 1995. 10. Bell Communications Research, TA-TSY-000773 - "Local Access System Generic Requirements, Objectives, and Interface in Support of Switched Multi-megabit Data Service" Issue 2, March 1990 and Supplement 1, December 1990. 11. ETS 300 269 Draft Standard T/NA(91)17 - "Metropolitan Area Network Physical Layer Convergence Procedure for 2.048 Mbit/s", April 1994. 12. ETS 300 270 Draft Standard T/NA(91)18 - "Metropolitan Area Network Physical Layer Convergence Procedure for 34.368 Mbit/s", April 1994. 13. ITU-T Recommendation O.151 - "Error Performance Measuring Equipment Operating at the Primary Rate and Above", October, 1992. 14. ITU-T Recommendation I.432 - "B-ISDN User-Network Interface - Physical Layer Specification", 1993 15. ITU-T Recommendation G.703 - "Physical/Electrical Characteristics of Hierarchical Digital Interfaces", 1991.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 7
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
16. ITU-T Recommendation G.704 - "General Aspects of Digital Transmission Systems; Terminal Equipments - Synchronous Frame Structures Used At 1544, 6312, 2048, 8488 and 44 736 kbit/s Hierarchical Levels", July, 1995. 17. ITU-T Recommendation G.751 - CCITT Blue Book Fasc. III.4, "Digital Multiplex Equipments Operating at the Third Order Bit Rate of 34,368 kbit/s and the Fourth Order Bit Rate of 139,264 kbit/s and Using Positive Justification", 1988. 18. ITU-T Draft Recommendation G.775 - "Loss of Signal (LOS) and Alarm Indication Signal (AIS) Defect Detection and Clearance Criteria", October 1993. 19. ITU-T Recommendation G.804 - "ATM Cell Mapping into Plesiochronous Digital Hierarchy (PDH)", 1993. 20. ITU-T Recommendation G.832 - "Transport of SDH Elements on PDH Networks: Frame and Multiplexing Structures", 1993. 21. ITU-T Recommendation Q.921 - "ISDN User-Network Interface - Data Link Layer Specification", March, 1993. 22. NTT Technical Reference, "NTT Technical Reference for High-Speed Digital Leased Circuit Services", 1991.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
4
APPLICATION EXAMPLES The S/UNI-QJET can be configured as an ATM physical layer device. On the line side, it connects to one or more J2/E3/T3 line interface units and on the system side, the S/UNI-QJET interfaces to the ATM layer device, such as PM7322 RCMP-800, over an 8 or 16 bit wide UTOPIA Level 2 interface (as shown in Figure 1). Figure 1 - S/UNI-QJET, as an ATM PHY, in an ATM Switch
T 1 /E 1 L in e C a rd O C -1 2 L in e C a rd
UT O P IA B us
PM 5355 S /U N I-6 2 2 PMD
PM 4314 QDSX
PM 7344 S /U N I-M P H
A T M S w itc h C o re J 2 /E 3 /T 3 L in e C a rd
J 2 /E3 /T 3 L IU S w itc h F a b ric
O C -3 L in e C a rd s
PM 5346 PM 5355 SS /U N I-6 2E /U N I-L IT 2
UT O P IA B us
J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU
PM 7346 PM 5355 PM 7346 SS /U N I-6 2 2T /U N I-Q J E T S /U N I-Q J E
PM 7322 R C M P -8 0 0
E g re s s D e vic e
PM 7348 PM 7348 S /U N I-D U A L S /U N I-D U A L PM 5347 PM 5355 S /U N N I-6 2 2 S /U I-P L U S
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
S/UNI-QJET can be configured as a quad J2/E3/T3 framer for use in router, frame relay switch and multiplexer applications (as shown in Figure 2). In an unchannelized J2/E3/T3 line card, S/UNI-QJET interfaces directly to one or more PM7366 FREEDM-8 HDLC controllers. Each FREEDM-8 can process two highspeed links, such as T3 and E3, or it can process up to eight lower speed links such as J2. The S/UNI-QJET can gap all the overhead bits such that only the payload data is passed to and from FREEDM-8. On the line side, S/UNI-QJET is connected to one or more J2/E3/T3 line interface units. On the system side, S/UNI-QJET interfaces with a data link device over a serial bit interface. In a PPP-Over-SONET application, the S/UNI-QJET interfaces to PM5342 SPECTRA-155 to map three T3 data streams onto three corresponding STS-1 services that are collectively carried over an OC-3 link. Figure 2 - S/UNI-QJET, as a Quad Framer Device, in Frame Relay Equipment
A C C E S S S ID E U P L IN K S ID E
U n ch a n n e lize d J 2 /E 3 /T 3 C a rd J 2 /E3 /T 3 L IU P M 73 4 6 P M 73 4 6 P M 53 5 5 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU J 2 /E3 /T 3 L IU P a c k e t O ve r S O N E T C a rd (3 D S -3 s O ve r O C -3 )
8 P o rt C h a n ne lize d T 1 C a rd
PCI Bus
PM43 4 43 PPM431144 PMM43114 QDSSX QQDSXX QDDSX
P M 43 8 8 P M 43 8 8 TO CTL TO CTL
PM 73 6 6 PPM736665 M 73 PM 73 646 FREEEDM D-8 FSREEEI-PM-8 F /U E DM-8H FRRENDDM -8
IP S w itch /R o u te r C o re
4 P o rt C h a n n e lize d E1 C a rd P M 43 1 4 P M 43 1 4 QDSX QDSX P M 63 4 4 P M 43 8 8 EQ UAD TO CTL P M 73 6 6 P M 73 4 5 F R EN I-P D H S /U E D M -8 S w itc h F ab ric
P M 73 6 6 P M 73 6 6 F R E E D M -8 F R E E D M -8
2 8 P o rt U n c h a n ne lize d T 1 C a rd (M 13 ) P M43 8 43 PPM43 88 8 PPM43 8888 PM M43888 M 43 8 TOC L TTOCTTL TTOCT TL TO OCTLL O CC L T D S -3 L IU P M 83 1 3 P M 83 1 3 D3MX D3MX P M 73 6 4 P M 73 4 5 FS /UE D M D H R E N I-P -3 2
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 10
PCI Bus
P ro ce s s o r
Packet M e m o ry
P M 73 6 6 F R E E D M -8 P M 73 6 6 F R E E D M -8
P M 73 4 6 S /U N I-Q J E T
P M 5 34 2 S P E C T R A -15 5
O p tic s
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
The S/UNI-QJET can be configured as a cell processor to provide cell mapping functions for xDSL modems in an ATM based Digital Subscriber Loop Access Multiplexer (DSLAM) equipment. As shown in Figure 3, each S/UNI-QJET provides four cell processors. Two S/UNI-QJETs are required in an 8 port xDSL line card. Figure 3 - S/UNI-QJET, as a Cell Processor, in DSLAM Equipment
U P L IN K S ID E
A C C E S S S ID E 8 P o rt x D S L C a rd
xD S L M o d e m
xD S L M o d e m
xD S L M o d e m
PM 7346 PM 7346 PM 5355 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E
A T M S w itc h C o re
S w itc h F a b ric
O C -3 L in e C a rd s
PM 5346 PM 5355 SS /U N I-6 2E /U N I-L IT 2 PM 7348 PM 7348 S /U N I-D U A L S /U N I-D U A L
xD S L M o d e m
xD S L M o d e m
xD S L M o d e m
xD S L M o d e m
PM 7346 PM 7346 PM 5355 S /U N I-Q J E T SS /U N I-6 2 2T /U N I-Q J E
PM 7322 R C M P -8 0 0
E g re s s D e v ic e
PM 5347 PM 5347 S /U N I-P L U S S /U N I-P L U S
U TO P IA B us
U TO P IA B us
xD S L M o d e m
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
5
BLOCK DIAGRAM Figure 4 - Normal Operating Mode
T P O H IN S [4:1] T P OH /T D AT I[4:1] T IO H M /T FP I/T M FP I[4:1] T IC LK [4:1] T P O H C LK [4:1] T P OH FP /T FP O /T MFP O /T GA P C LK /T C E LL[4:1] R E F8K I
T O H IN S [4:1] T O H [4:1] T O H C LK [4:1] T O H FP [4:1]
XBOC Tx FE A C
TDPR Tx H D LC
Tx 1 /2 T T B O /H T x T rail A ccess B uffer
IE E E P 1149.1 JT A G T est A ccess P ort
TMS
TRSTB
TDO
TCK
TDI
D T C A [4:1] T D A T [15:0] TPRTY TSOC TCA T A D R [4:0] TENB T FCLK S ystem I/F P H Y_A D R [2:0] ATM8 R FC LK RENB R A D R [4:0] RCA RSOC RPRTY R D A T [15:0] D R C A [4:1]
T P OS /T D AT O [4:1] TNEG/TOHM[4:1] T C LK [4:1]
Line E ncode
R C LK [4:1] R PO S /RD A TI[4:1] R N E G /R LC V /R O H M [4:1]
FRM R J2, E 3, or D S3 Line R eceive D ecode Fram er
P R G D B E R T ester
T RAN J2, E 3, or D S3 T ransm it Fram er
S P LT T ransm it A T M and P LC P Fram er
T X C P_ 5 0 Tx C ell P rocessor
T X FF Tx 4 C ell FIFO
AT M F /S P L R R eceiv e A T M and PLC P Fram er
RXCP_50 Rx C ell P rocessor
RXFF Rx 4 C ell FIFO
RBOC Rx FE A C
Rx RDLC PM O N 1 /2 T T B O /H Rx P erf. R x T rail H D LC M onitor A ccess B uffer
CPPM P LC P /cell P erf. M onitor
M icroprocess or I/F
LC D /R D AT O [4:1] R P O H /R O V R H D [4:1]] R E F8K O /R P O H F P /R FP O /R M FP O [4:1] R P O H C LK /R SC LK /R GA P C LK [4:1] FR MS T A T [4:1]
R O H [4:1] R O H C LK [4:1] R O H FP [4:1]
A [10:0] A LE
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D [7:0]
CSB W RB RDB RSTB IN T B
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Figure 5
- DS3/E3/J2 Framers Bypassed
T PO H INS [4:1] T PO H [4:1] T IOH M [4:1] T IC LK [4:1] T PO H CLK [4:1] T PO H FP[4:1] R EF8KI
XBOC Tx FE AC
TDPR Tx H DLC
Tx 1 /2 T T B O /H T x T rail Access Buffer
IE E E P 1149.1 JT A G T est A ccess P ort
TMS
T R ST B
TDO
TCK
TDI
D T CA [4:1] T D A T [15:0] TPRTY TSOC TCA T A D R [4:0] TENB T FCLK S ystem I/F PH Y_A DR [2:0] ATM8 R FC LK RENB R A D R[4:0] R CA RSOC RPRTY R DA T [15:0] D RC A[4:1]
T D AT O [4:1] TOHM[4:1] T C LK [4:1]
Line Encode
R CLK [4:1] R DA T I[4:1] R O H M[4:1]
Line D ecode
FR M R J2, E3, or DS3 R eceive Fram er
A T M F /S P L R R eceive AT M and PLC P Fram er
P R G D BE R T ester
T RA N J2, E3, or DS3 T ransm it Fram er
S P LT T ransm it AT M and PLC P Fram er
T X C P_ 5 0 Tx C ell P rocessor
T X FF Tx 4 Cell FIFO
RXCP_50 Rx C ell P rocessor
R XFF Rx 4 Cell FIFO
RBO C Rx FE AC
Rx RDLC PMO N 1 /2 T T B O /H Rx Perf. R x T rail H DLC M onitor Access B uffer
CPPM PLC P /cell P erf. M onitor
M icroprocessor I/F
LC D[4:1] R PO H[4:1] R PO HF P[4:1] R PO HC LK[4:1]
FR MST A T [4:1]
A[10:0] ALE
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C SB W RB R DB R ST B IN T B
D [7:0]
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Figure 6
- DS3/E3/J2 Transceiver Mode
T FPO /T M FPO /T G APC LK/TC ELL[4:1]
T D AT I[4:1] T FPI/TM FPI[4:1] T ICLK[4:1]
T O H IN S[4:1] T O H [4:1] T O H CLK[4:1] T O H FP[4:1]
XBOC Tx FEA C
TDPR Tx H DLC
Tx 1 /2 T T B O /H T x T rail Access Buffer
IEEE P 1149.1 JT AG T est Access Port
T POS/T D AT O [4:1] TNEG/TOHM[4:1] T C LK[4:1]
Line Encode
P R G D BER Tester
T RA N J2, E 3, or D S3 T ransm it Fram er
S P LT T ransm it AT M and P LC P Fram er
T X C P_ 50 Tx C ell Processor
TMS
T R ST B
T X FF Tx 4 C ell FIFO
TDO
TCK
TDI
System I/F
R X C P _5 0 Rx C ell Processor R X FF Rx 4 C ell FIFO
R CLK[4:1] R PO S/R DA T I[4:1] R NE G /R LCV [4:1]
FRMR J2, E 3, or D S3 Line R eceiv e D ecode Fram er
A T M F /S P L R R eceiv e AT M and PLCP Fram er
RBO C Rx FEA C
Rx R DL C P M O N 1 /2 T T B O /H Rx Perf. R x T rail H DLC M onitor Access Buffer
CPPM PLC P/cell Perf. M onitor
M icroprocessor I/F
R DA T O [4:1] R O VR HD [4:1] R EF8KO /R FPO /RM FPO[4:1] R SC LK/R G APC LK[4:1] FR MST AT [4:1]
R O H[4:1] R O HC LK[4:1] R O HFP [4:1]
A[10:0] ALE
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C SB W RB R DB R ST B INT B
D [7:0]
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Figure 7
- Loopback Modes
T P O H C LK [4:1] T P OH FP /T FP O /T MFP O /T GA P C LK /T C E LL[4:1] R E F8K I
T O H IN S [4:1] T O H [4:1] T O H C LK [4:1] T O H FP [4:1]
T P O H IN S [4:1] T P OH /T D AT I[4:1] T IO H M /T FP I/T M FP I[4:1] T IC LK [4:1]
Line
D iagnostic
XBOC Tx FE A C
TDPR Tx H D LC
Tx 1 /2 T T B O /H T x T rail A ccess B uffer P ayload
IE E E P 1149.1 JT A G T est A ccess P ort
TMS
TRSTB
TDO
TCK
TDI
D T C A [4:1] T D A T [15:0] TPRTY TSOC TCA T A D R [4:0] TENB T FCLK S ystem I/F P H Y _A D R [2:0] ATM8 R FC LK RENB R A D R [4:0] RCA RSOC RPRTY R D A T [15:0] D R C A [4:1]
T P OS /T D AT O [4:1] TNEG/TOHM[4:1] T C LK [4:1]
Line E ncode
R C LK [4:1] R P O S /R D A T I[4:1] R N E G /R LC V /R O H M [4:1]
Line D ecode
FRM R J2, E 3, or D S3 R eceive Fram er
P R G D B E R T ester
T RAN J2, E 3, or D S3 T ransm it Fram er
S P LT ing T im T ransm it A T M and P LC P Fram er
T X C P_ 5 0 Tx C ell P rocessor
T X FF Tx 4 C ell FIFO
AT M F /S P L R R eceiv e A T M and PLC P Fram er
RXCP_50 Rx C ell P rocessor
RXFF Rx 4 C ell FIFO
RBOC Rx FE A C
Rx RDLC PMON 1 /2 T T B O /H Rx P erf. R x Trail H D LC M onitor A ccess B uffer
CPPM P LC P /cell P erf. M onitor
M icroprocessor I/F
LC D /R D A T O [4:1] R P O H /R O V R H D [4:1] R E F8K O /R P O H FP /R FP O /R M FP O [4:1] R P O H C LK /R S C LK /R GA P C LK [4:1] FR MS T A T [4:1]
R O H [4:1] R O H C LK [4:1] R O H F P [4:1]
A [10:0] A LE
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D [7:0]
CSB W RB RDB RSTB IN T B
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
6
DESCRIPTION The PM7346 S/UNI-QJET is a quad ATM physical layer processor with integrated DS3, E3, and J2 framers. PLCP sublayer DS1, DS3, E1, and E3 processing is supported as is ATM cell delineation. The S/UNI-QJET contains integral DS3 framers, which provide DS3 framing and error accumulation in accordance with ANSI T1.107, and T1.107a, integral E3 framers, which provide E3 framing in accordance with ITU-T Recommendations G.832 and G.751, and integral J2 framers, which provide J2 framing in accordance with ITU-T Recommendation G.704 and I.432. When configured for DS3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both digital B3ZS-encoded bipolar and unipolar signals compatible with M23 and C-bit parity applications. When configured for E3 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both HDB3-encoded bipolar and unipolar signals compatible with G.751 and G.832 applications. When configured for J2 transmission system sublayer processing, the S/UNI-QJET accepts and outputs both B8ZS-encoded bipolar and unipolar signals compliant with G.704 and NTT 6.312 Mbit/s applications. When configured for DS1, or E1 transmission system sublayer processing, the S/UNI-QJET accepts and outputs unipolar signals with appropriate clock and frame pulse signals for physical sublayer processing. When configured for other transmission systems, the S/UNI-QJET provides a generic interface for physical sublayer processing. In the DS3 receive direction, the S/UNI-QJET frames to DS3 signals with a maximum average reframe time of 1.5 ms and detects line code violations, loss of signal, framing bit errors, parity errors, path parity errors, AIS, far end receive failure and idle code. The DS3 overhead bits are extracted and presented on serial outputs. When in C-bit parity mode, the Path Maintenance Data Link and the Far End Alarm and Control (FEAC) channels are extracted. HDLC receivers are provided for Path Maintenance Data Link support. In addition, valid bitoriented codes in the FEAC channels are detected and are available through the microprocessor port. In the E3 receive direction, the S/UNI-QJET frames to G.751 and G.832 E3 signals with a maximum average reframe times of 135s for G.751 frames and 250s for G.832 frames. Line code violations, loss of signal, framing bit errors,
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
AIS, and remote alarm indication are detected. Further, when processing G.832 formatted data, parity errors, far end receive failure, and far end block errors are also detected; and the Trail Trace message may be extracted and made available through the microprocessor port. HDLC receivers are provided for either the G.832 Network Requirement or the G.832 General Purpose Data Link support. In the J2 receive direction, the S/UNI-QJET frames to G.704 6.312 MHz signals with a maximum average reframe time of 5.07ms. An alternate framing algorithm which uses the CRC-5 bits to rule out 99.9% of all static mimic framing patterns is available with a maximum average reframe time of 10.22ms when operating with a 10-4 bit error rate. The alternate framing algorithm can be selected via the CRC_REFR bit in the J2-FRMR Configuration Register. Line code violations, loss of signal, loss of frame, framing bit errors, physical layer AIS, payload AIS, CRC-5 errors, Remote End Alarm, and Remote Alarm Indication are detected. HDLC receivers are provided for Data Link support. Error event accumulation is also provided by the S/UNI-QJET. Framing bit errors, line code violations, parity errors, path parity errors and far end block errors are accumulated, when appropriate, in saturating counters for DS3, E3, and J2 frames. Loss of Frame detection for DS3, E3, and J2 is provided as recommended by ITU-T G.783 with integration times of 1ms, 2ms, and 3ms. In the DS3 transmit direction, the S/UNI-QJET inserts DS3 framing, X and P bits. When enabled for C-bit parity operation, bit-oriented code transmitters and HDLC transmitters are provided for insertion of the FEAC channels and the Path Maintenance Data Links into the appropriate overhead bits. Alarm Indication Signals can be inserted by using internal register bits; other status signals such as the idle signal can be inserted when enabled by internal register bits. When M23 operation is selected, the C-bit Parity ID bit (the first C-bit of the first M subframe) is forced to toggle so that downstream equipment will not confuse an M23-formatted stream with stuck-at 1 C-bits for C-bit Parity application. In the E3 transmit direction, the S/UNI-QJET inserts E3 framing in either G.832 or G.751 format. When enabled for G.832 operation, an HDLC transmitter is provided for insertion of either the Network Requirement or General Purpose Data Link into the appropriate overhead bits. The Alarm Indication Signal and other status signals can be inserted by internal register bits. In the J2 transmit direction, the S/UNI-QJET inserts J2 6.312 Mbit/s G.704 framing. HDLC transmitter are provided for insertion of the Data Links. CRC-5 check bits are calculated and inserted into the J2 multiframe. External pins are provided to enable overwriting of any of the overhead bits within the J2 frame.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
The S/UNI-QJET also supports diagnostic options which allow it to insert, when appropriate for the transmit framing format, parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, all-zeros, AIS, Remote Alarm Indications, and Remote End Alarms. The S/UNI-QJET provides cell delineation for ATM cells using the PLCP framing format, or by using the header check sequence octet in the ATM cell header as specified by ITU-T Recommendation I.432. DS1, DS3, E1 and E3 based PLCP frame formats can be processed. Non-PLCP-based cell delineation is accomplished with either bit, nibble, or byte-wide search algorithms, depending on the line interface used. An interface consistent with the generic physical interface defined by ITU-T Recommendation I.432 is provided for arbitrary rates up to 52 Mbit/s. This interface is used to provide physical layer support for transmission systems that do not have an associated PLCP sublayer, or to provide an efficient means of directly mapping ATM cells to existing transmission system formats (such as DS3 and DS1). In the PLCP receive direction, framing, path overhead extraction and cell extraction is provided. BIP-8 error events, frame octet error events and far end block error events are accumulated. In the PLCP transmit direction, the S/UNI-QJET provides overhead insertion using inputs or internal registers, DS3 nibble and E3 byte stuffing, automatic BIP8 octet generation and insertion and automatic far end block error insertion. Diagnostic features for BIP-8 error, framing error and far end block error insertion are also supported. In the cell receive path, idle cells may be dropped according to a programmable filter. By default, incoming cells with single bit HCS errors are corrected and written to the FIFO buffer. Optionally, cells can be dropped upon detection of a HCS error. Cell delineation may optionally be disabled to allow passing of all cells, regardless of cell delineation status. The ATM cell payloads are optionally descrambled. ATM cell headers may optionally be descrambled (for use with PPP packets). Assigned cells containing no detectable HCS errors are written to a FIFO buffer. Cells data is read from the FIFO using a synchronous 50 MHz 8bit wide or 16-bit wide SCI-PHYTM and Utopia Level 2 compatible interface. Cell data parity is also provided. Counts of error-free assigned cells, and cells containing HCS errors are accumulated independently for performance monitoring purposes. In the cell transmit path, cell data is written to a FIFO buffer using a synchronous 50 MHz 8-bit wide or 16-bit wide SCI-PHYTM compatible interface. Cell data parity is also examined for errors. Idle cells are automatically inserted when the FIFO contains less than one full cell. HCS generation, cell payload scrambling,
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
and cell header scrambling (for use with PPP packets) are optionally provided. Counts of transmitted cells are accumulated for performance monitoring purposes. Both receive and transmit cell FIFOs provide buffering for four cells. The FIFOs provide the rate matching interface between the higher layer ATM entity and the S/UNI-QJET. The S/UNI-QJET is configured, controlled and monitored via a generic 8-bit microprocessor bus through which all internal registers are accessed. All sources of interrupts can be identified, acknowledged, or masked via this interface.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
7
PIN DIAGRAM The S/UNI-QJET is packaged in a 256-pin SBGA package having a body size of 27mm by 27mm and a pin pitch of 1.27 mm.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
8
PIN DESCRIPTION Pin Name TPOS[4] TPOS[3] TPOS[2] TPOS[1] Type Output Pin No. C6 B4 D3 F2 Function Transmit Digital Positive Pulse (TPOS[4:1]). TPOS[4:1] contains the positive pulses transmitted on the B3ZSencoded DS3, HDB3-encoded E3, or B8ZS-encoded J2 transmission system when the dual-rail output format is selected. Transmit Data (TDATO[4:1]). TDATO[4:1] contains the transmit data stream when the single-rail (unipolar) output format is enabled or when a non-DS3/E3/J2 based transmission system is selected. The TPOS/TDATO[4:1] pin function selection is controlled by the TFRM[1:0] and the TUNI bits in the S/UNI-QJET Transmit Configuration Registers. Output signal polarity control is provided by the TPOSINV bit in the S/UNI-QJET Transmit Configuration Registers. Both TPOS[4:1] and TDATO[4:1] are updated on the falling edge of TCLK[4:1] by default, and may be configured to be updated on the rising edge of TCLK[4:1] through the TCLKINV bit in the S/UNI-QJET Transmit Configuration Registers. Finally, both TPOS[4:1] and TDATO[4:1] can be updated on the rising edge of TICLK[4:1], enabled by the TICLK bit in the S/UNI-QJET Transmit Configuration Registers. TNEG[4] TNEG[3] TNEG[2] TNEG[1] Output A5 D5 E4 F1 Transmit Digital Negative Pulse (TNEG[4:1]). TNEG[4:1] contains the negative pulses transmitted on the B3ZSencoded DS3, HDB3-encoded E3, or B8ZS-encoded J2 transmission system when the dual-rail NRZ output format is selected.
TDATO[4] TDATO[3] TDATO[2] TDATO[1]
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TOHM[4] TOHM[3] TOHM[2] TOHM[1]
Type Output
Pin No. A5 D5 E4 F1
Function Transmit Overhead Mask (TOHM[4:1]). TOHM[4:1] indicates the position of overhead bits (non-payload bits) in the transmission system stream aligned with TDATO[4:1]. TOHM[4:1] indicates the location of the M-frame boundary for DS3, the position of the frame boundary for E3, and the position of the multi-frame boundary for J2 when the single-rail (unipolar) NRZ input format is enabled. When a PLCP formatted signal is transmitted, TOHM[4:1] is set to logic 1 once per transmission frame, and indicates the DS1 or E1 frame alignment. When a non-PLCP non-DS3, non-E3, non, J2 based signal is transmitted, TOHM[4:1] is a delayed version of the TIOHM[4:1] input, and indicates the position of each overhead bit in the transmission frame. TOHM[4:1] is updated on the falling edge of TCLK[4:1]. The TNEG/TOHM[4:1] pin function selection is controlled by the TFRM[1:0] and the TUNI bits in the S/UNI-QJET Transmit Configuration Registers. Output signal polarity control is provided by the TNEGINV bit in the S/UNI-QJET Transmit Configuration Registers. Both TNEG[4:1] and TOHM[4:1] are updated on the falling edge of TCLK[4:1] by default, and may be enabled to be updated on the rising edge of TCLK[4:1]. This sampling is controlled by the TCLKINV bit in the S/UNI-QJET Transmit Configuration Registers. Finally, both TNEG[4:1] and TOHM[4:1] can be updated on the rising edge of TICLK[4:1], enabled by the TICLK bit in the S/UNI-QJET Transmit Configuration Registers.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TCLK[4] TCLK[3] TCLK[2] TCLK[1]
Type Output
Pin No. B5 C4 D2 G3
Function Transmit Output Clock (TCLK[4:1]). TCLK[4:1] provides the transmit direction timing. TCLK[4:1] is a buffered version of TICLK[4:1] and can be enabled to update the TPOS/TDATO[4:1] and TNEG/TOHM[4:1] outputs on its rising or falling edge. Receive Digital Positive Pulse (RPOS[4:1]). RPOS[4:1] contains the positive pulses received on the B3ZSencoded DS3, the HDB3-encoded E3, or the B8ZS-encoded J2 transmission system when the dual-rail NRZ input format is selected. Receive Data (RDATI[4:1]). RDATI[4:1] contains the data stream when the singlerail (unipolar) NRZ input format is enabled or when a non-DS3/E3/J2 based transmission system is being processed (for example RDATI may contain a DS1 or E1 stream). The RPOS/RDATI[4:1] pin function selection is controlled by the RFRM[1:0] bits in the S/UNI-QJET Configuration Registers and by the UNI bits in the DS3 FRMR, the E3 FRMR, or the J2 FRMR Configuration Registers. Both RPOS[4:1] and RDATI[4:1] are sampled on the rising edge of RCLK[4:1] by default, and may be enabled to be sampled on the falling edge of RCLK[4:1]. This sampling is controlled by the RCLKINV bit in the S/UNI-QJET Receive Configuration Registers. In addition, signal polarity control is provided by the RPOSINV bit in the S/UNI-QJET Receive Configuration Registers.
RPOS[4] RPOS[3] RPOS[2] RPOS[1]
Input
D6 D1 E2 H4
RDATI[4] RDATI[3] RDATI[2] RDATI[1]
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name RNEG[4] RNEG[3] RNEG[2] RNEG[1]
Type Input
Pin No. C5 E3 E1 G2
Function Receive Digital Negative Pulse (RNEG[4:1]). RNEG[4:1] contains the negative pulses received on the B3ZS encoded DS3, the HDB3-encoded E3, or the B8ZS-encoded J2 transmission system when the dual-rail NRZ input format is selected. Receive Line Code Violation (RLCV[4:1]). RLCV[4:1] contains line code violation indications when the single-rail (unipolar) NRZ input format is enabled for DS3, E3, or J2 applications. Each line code violation is represented by an RCLK[4:1] period-wide pulse.
RLCV[4] RLCV[3] RLCV[2] RLCV[1]
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name ROHM[4] ROHM[3] ROHM[2] ROHM[1]
Type Input
Pin No. C5 E3 E1 G2
Function Receive Overhead Mask (ROHM[4:1]). When a DS1 or E1 PLCP or ATM directmapped signal is received, ROHM[4:1] is pulsed once per transmission frame, and indicates the DS1 or E1 frame alignment relative to the RDATI[4:1] data stream. When an alternate frame-based signal is received, ROHM[4:1] indicates the position of each overhead bit in the transmission frame. The RNEG/RLCV/ROHM[4:1] pin function selection is controlled by the RFRM[1:0] bits in the S/UNI-QJET Receive Configuration Registers, the UNI bits in the DS3 FRMR, E3 FRMR, or J2 FRMR Configuration Registers, and the PLCPEN and EXT bits in the SPLR Configuration register. RNEG[4:1], RLCV[4:1], and ROHM[4:1] are sampled on the rising edge of RCLK[4:1] by default, and may be enabled to be sampled on the falling edge of RCLK[4:1]. This sampling is controlled by the RCLKINV bit in the S/UNI-QJET Receive Configuration Registers. In addition, signal polarity control is provided by the RNEGINV bit in the S/UNI-QJET Receive Configuration Registers.
RCLK[4] RCLK[3] RCLK[2] RCLK[1]
Input
A4 F4 F3 G1
Receive Clock (RCLK[4:1]). RCLK[4:1] provides the receive direction timing. RCLK[4:1] is the externally recovered transmission system baud rate clock that samples the RPOS/RDATI[4:1] and RNEG/RLCV/ROHM[4:1] inputs on its rising or falling edge.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 25
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TOHINS[4] TOHINS[3] TOHINS[2] TOHINS[1]
Type Input
Pin No. J4 K2 M4 R1
Function Transmit DS3/E3/J2 Overhead Insertion (TOHINS[4:1]). TOHINS[4:1] controls the insertion of the DS3, E3, or J2 overhead bits from the TOH[4:1] input. When TOHINS[4:1] is high, the associated overhead bit in the TOH[4:1] stream is inserted in the transmitted DS3, E3, or J2 frame. When TOHINS[4:1] is low, the DS3, E3, or J2 overhead bit is generated and inserted internally. TOHINS[4:1] is sampled on the rising edge of TOHCLK[4:1]. If TOHINS[4:1] is a logic 1, the TOH[4:1] input has precedence over the internal datalink transmitter, or any internal register bit setting.
PMC-SIERRA, INC. PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA INC., AND ITS CUSTOMERS' INTERNAL USE 26
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TOH[4] TOH[3] TOH[2] TOH[1]
Type Input
Pin No. H3 K3 N1 P3
Function Transmit DS3/E3/J2 Overhead Data (TOH[4:1]). When configured for DS3 operation, TOH[4:1] contains the overhead bits (C, F, X, P and M) that may be , inserted in the transmit DS3 stream. When configured for G.832 E3 operation, TOH[4:1] contains the overhead bytes (FA1, FA2, EM mask, TR, MA, NR, and GC) that may be inserted in the transmit G.832 E3 stream. When configured for G.751 E3 operation, TOH[4:1] contains the overhead bits (RAI, National Use, Stuff Indication, and Stuff Opportunity) that may be inserted in the transmit G.751 E3 stream. When configured for J2 operation, TOH[4:1] contains the overhead bits (TS97, TS98, Framing, X1-3, A, M, E1-5) that may be inserted in the transmit J2 stream. If TOHINS[4:1] is a logic 1, the TOH[4:1] input has precedence over the internal datalink transmitter, or any other internal register bit setting. TOH[4:1] is sampled on the rising edge of TOHCLK[4:1].
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TOHFP[4] TOHFP[3] TOHFP[2] TOHFP[1]
Type Output
Pin No. J3 L3 N3 R3
Function Transmit DS3/E3/J2 Overhead Frame Position (TOHFP[4:1]). TOHFP[4:1] is used to align the individual overhead bits in the transmit overhead data stream, TOH[4:1], to the DS3 M-frame or the E3 frame. For DS3, TOHFP[4:1] is high during the X1 overhead bit position in the TOH[4:1] stream. For G.832 E3, TOHFP[4:1] is high during the first bit of the FA1 byte. For G.751 E3, TOHFP[4:1] is high during the RAI overhead bit position in the TOH[4:1] stream. For J2, TOHFP[4:1] is high during the first bit of timeslot 97 in the first frame of a 4-frame multiframe). TOHFP[4:1] is updated on the falling edge of TOHCLK[4:1]. Transmit DS3/E3/J2 Overhead Clock (TOHCLK[4:1]). TOHCLK[4:1] is active when a DS3, E3, or J2 stream is being processed. TOHCLK[4:1] is nominally a 526 kHz clock for DS3, a 1.072 MHz clock for G.832 E3, a 1.074 MHz clock for G.751 E3, and a gapped 6.312 MHz clock with an average frequency of 168 kHz for J2. TOHFP[4:1] is updated on the falling edge of TOHCLK[4:1]. TOH[4:1], and TOHINS[4:1] are sampled on the rising edge of TOHCLK[4:1].
TOHCLK[4] TOHCLK[3] TOHCLK[2] TOHCLK[1]
Output
H2 K1 N2 R2
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name REF8KI
Type Input
Pin No. T3
Function Reference 8 kHz Input (REF8KI). The PLCP frame rate is locked to an external 8 kHz reference applied on this input . An internal phase-frequency detector compares the transmit PLCP frame rate with the externally applied 8 kHz reference and adjusts the PLCP frame rate. The REF8KI input must transition high once every 125 s for correct operation. The REF8KI input is treated as an asynchronous signal and must be "glitchfree". If the LOOPT register bit is logic 1, the PLCP frame rate is locked to the RPOHFP[x] signal instead of the REF8KI input.
TPOHINS[4] TPOHINS[3] TPOHINS[2] TPOHINS[1]
Input
V14 W11 U9 W5
Transmit Path Overhead Insertion (TPOHINS[4:1]). TPOHINS[4:1] controls the insertion of PLCP overhead octets on the TPOH[4:1] input. When TPOHINS[4:1] is logic 1, the associated overhead bit in the TPOH[4:1] stream is inserted in the transmit PLCP frame. When TPOHINS[4:1] is logic 0, the PLCP path overhead bit is generated and inserted internally. TPOHINS[4:1] is sampled on the rising edge of TPOHCLK[4:1]. Note, when operating in G.751 E3 PLCP mode, bits 8, 7 and 6 of the C1 octet should not be manipulated.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TPOH[4] TPOH[3] TPOH[2] TPOH[1]
Type Input
Pin No. Y15 W12 W8 Y5
Function Transmit PLCP Overhead Data (TPOH[4:1]). TPOH[4:1] is valid when the FRMRONLY bit in the S/UNI-QJET Configuration 1 registers is logic 0. TPOH[4:1] contains the PLCP path overhead octets (Zn, F1, B1, G1, M1, M2, and C1) which may be inserted in the transmit PLCP frame. The octet data on TPOH[4:1] is shifted in order from the most significant bit (bit 1) to the least significant bit (bit 8). TPOH[4:1] is sampled on the rising edge of TPOHCLK[4:1]. Framer Transmit Data (TDATI[4:1]). TDATI[4:1] contains the serial data to be transmitted when the S/UNI-QJET is configured as a DS3, E3, or J2 framer device for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Register. TDATI[4:1] is sampled on the rising edge of TICLK[4:1] if the TXGAPEN register bit in the S/UNI-QJET Configuration 2 register is logic 0. If TXGAPEN is logic 1, then TDATI[4:1] is sampled on the falling edge of TGAPCLK[4:1].
TDATI[4] TDATI[3] TDATI[2] TDATI[1]
TPOHFP[4] TPOHFP[3] TPOHFP[2] TPOHFP[1]
Output
W14 Y10 Y7 V5
Transmit Path Overhead Frame Position (TPOHFP[4:1]). TPOHFP[4:1] is valid when the FRMRONLY bit in the S/UNI-QJET Configuration 1 Registers is logic 0. The TPOHFP[4:1] output locates the individual PLCP path overhead bits in the transmit overhead data stream, TPOH[4:1]. TPOHFP[4:1] is logic 1 while bit 1 (the most significant bit) of the path user channel octet (F1) is present in the TPOH[4:1] stream. TPOHFP[4:1] is updated on the falling edge of TPOHCLK[4:1].
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TFPO[4] TFPO[3] TFPO[2] TFPO[1]
Type Output
Pin No. W14 Y10 Y7 V5
Function Framer Transmit Frame Pulse/Multi-frame Pulse Reference (TFPO/TMFPO[4:1]). TFPO/TMFPO[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Registers to logic 1 and the TXGAPEN bit in the S/UNI-QJET Configuration Registers to logic 0. TFPO[4:1] pulses high for 1 out of every 85 clock cycles when configured for DS3, giving a free-running mark for all overhead bits in the frame. TFPO[4:1] pulses high for 1 out of every 1536 clock cycles when configured for G.751 E3, giving a freerunning reference G.751 indication. TFPO[4:1] pulses high for 1 out of every 4296 clock cycles when configured for G.832 E3, giving a free-running reference G.832 frame indication. TFPO[4:1] pulses high for 1 out of every 789 clock cycles when configured for J2, giving a freerunning reference frame indication.
TMFPO[4] TMFPO[3] TMFPO[2] TMFPO[1]
TMFPO[4:1] pulses high for 1 out of every 4760 clock cycles when configured for DS3, giving a free-running reference Mframe indication. TMFPO[4:1] pulses high for 1 out of every 3156 clock cycles when configured for J2, giving a free-running reference multi-frame indication. TMFPO[4:1] behaves the same as TFPO[4:1] for E3 applications. TFPO/TMFPO[4:1] is updated on the rising edge of TICLK[4:1] or RCLK[4:1] if loop-timed.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TGAPCLK[4] TGAPCLK[3] TGAPCLK[2] TGAPCLK[1]
Type Output
Pin No. W14 Y10 Y7 V5
Function Framer Gapped Transmit Clock (TGAPCLK[4:1]). TGAPCLK[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Registers and the TXGAPEN bit in the S/UNI-QJET Configuration 2 Registers. TGAPCLK[4:1] is derived from the transmit reference clock TICLK[4:1] or from the receive clock if loop-timed. The overhead bit (gapped) positions are generated internal to the device. TGAPCLK[4:1] is held high during the overhead bit positions. This clock is useful for interfacing to devices which source payload data only. TGAPCLK[4:1] is used to sample TDATI[4:1].
TCELL[4] TCELL[3] TCELL[2] TCELL[1]
Transmit Cell Indication (TCELL[4:1]). TCELL[x] is valid when the TCELL bit in the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH) is set. TCELL[x] pulses once for every cell (idle or assigned) transmitted. TCELL[x] is updated using timing derived from the transmit input clock (TICLK[x]), and is active for a minimum of 8 TICLK[x] periods (or 8 RCLK[x] periods if loop-timed).
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TPOHCLK[4] TPOHCLK[3] TPOHCLK[2] TPOHCLK[1]
Type Output
Pin No. U13 V11 V8 U6
Function Transmit PLCP Overhead Clock (TPOHCLK[4:1]). TPOHCLK[4:1] is active when PLCP processing is enabled. TPOHCLK[4:1] is nominally a 26.7 kHz clock for a DS1 PLCP frame, a 768 kHz clock for a DS3 PLCP frame, a 33.7 kHz clock for an E1 based PLCP frame, and a 576 kHz clock for an G.751 E3 based PLCP frame. TPOHFP[4:1] is updated on the falling edge of TPOHCLK[4:1]. TPOH[4:1], and TPOHINS[4:1] are sampled on the rising edge of TPOHCLK[4:1]. Transmit Input Overhead Mask (TIOHM[4:1]). TIOHM[4:1] is valid only if the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is logic 0. TIOHM[4:1] indicates the position of overhead bits when not configured for DS1, DS3, E1, E3, or J2 transmission system streams. TIOHM[4:1] is delayed internally to produce the TOHM[4:1] output. When configured for operation over a DS1, a DS3, an E1, an E3, or a J2 transmission system sublayer, TIOHM[4:1] is not required, and should be set to logic 0. When configured for other transmission systems, TIOHM[4:1] is set to logic 1 for each overhead bit position. TIOHM[4:1] is set to logic 0 if the transmission system contains no overhead bits. TIOHM[4:1] is sampled on the rising edge of TICLK[4:1].
TIOHM[4] TIOHM[3] TIOHM[2] TIOHM[1]
Input
W15 V12 V9 V6
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TFPI[4] TFPI[3] TFPI[2] TFPI[1]
Type Input
Pin No. W15 V12 V9 V6
Function Framer Transmit Frame Pulse/Multiframe Pulse (TFPI/TMFPI[4:1]). TFPI/TMFPI[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Register to logic 1. TFPI[4:1] indicates the position of all overhead bits in each DS3 M-subframe, the first bit in each G.751 E3 or G.832 E3 frame, or the first framing bit in each J2 frame. TFPI[4:1] is not required to pulse at every frame boundary in E3 or J2 modes.
TMFPI[4] TMFPI[3] TMFPI[2] TMFPI[1]
TMFPI[4:1] indicates the position of the first bit in each DS3 M-frame, the first bit in each E3 frame, or the first framing bit in each J2 multiframe. TMFPI[4:1] is not required to pulse at every multiframe boundary. TFPI/TMFPI[4:1] is sampled on the rising edge of TICLK[4:1].
TICLK[4] TICLK[3] TICLK[2] TICLK[1]
Input
V15 Y13 W9 W6
Transmit Input Clock (TICLK[4:1]). TICLK[4:1] provides the transmit direction timing. TICLK[4:1] is the externally generated transmission system baud rate clock. It is internally buffered to produce the transmit clock output, TCLK[4:1], and can be enabled to update the TPOS/TDATO[4:1] and TNEG/TOHM[4:1] outputs on the TICLK[4:1] rising edge. The TICLK[4:1] maximum frequency is 52 MHz.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name ROHFP[4] ROHFP[3] ROHFP[2] ROHFP[1]
Type Output
Pin No. J1 M2 P2 T2
Function Receive DS3/E3/J2 Overhead Frame Position (ROHFP[4:1]). ROHFP[4:1] locates the individual overhead bits in the received overhead data stream, ROH[4:1]. ROHFP[4:1] is high during the X1 overhead bit position in the ROH[4:1] stream when processing a DS3 stream. ROHFP[4:1] is high during the first bit of the FA1 byte when processing a G.832 E3 stream. ROHFP[4:1] is high during the RAI overhead bit position when processing a G.751 E3 stream. ROHFP[4:1] is high during the first bit in Timeslot 97 in the first frame of the 4-frame multiframe when processing a J2 stream. ROHFP[4:1] is updated on the falling edge of ROHCLK[4:1]. Receive DS3/E3/J2 Overhead Data (ROH[4:1]). ROH[4:1] contains the overhead bits (C, F, X, P and M) extracted , from the received DS3 stream; ROH[4:1] contains the overhead bytes (FA1, FA2, EM, TR, MA, NR, and GC) extracted from the received G.832 E3 stream; ROH[4:1] contains the overhead bits (RAI, National Use, Stuff Indication, and Stuff Opportunity) extracted from the received G.751 E3 stream; ROH[4:1] contains the overhead bits (Framing, X1-3, A, M, E1-5) extracted from the received J2 stream. ROH[4:1] is updated on the falling edge of ROHCLK[4:1].
ROH[4] ROH[3] ROH[2] ROH[1]
Output
J2 L2 P1 T1
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name ROHCLK[4] ROHCLK[3] ROHCLK[2] ROHCLK[1]
Type Output
Pin No. K4 M3 N4 R4
Function Receive DS3/E3/J2 Overhead Clock (ROHCLK[4:1]). ROHCLK[4:1] is active when a DS3, E3, or J2 stream is being processed. ROHCLK[4:1] is nominally a 526 kHz clock when processing DS3, a 1.072 MHz clock when processing G.832 E3, a 1.074 MHz clock when processing G.751 E3, and a gapped 6.312 MHz clock with an average frequency of 168 kHz for J2. ROH[4:1], and ROHFP[4:1] are updated on the falling edge of ROHCLK[4:1]. Reference 8kHz Output (REF8KO[4:1]). REF8KO[4:1] is an 8kHz reference derived from the receive clocks on RCLK[4:1]. A free-running divide-down counter is used to generate REF8KO[4:1] so it will not glitch on reframe actions. REF8KO[4:1] will pulse high for approximately 1 RCLK[4:1] cycle every 125 s. REF8KO[4:1] should be treated as a glitch-free asynchronous signal. Receive PLCP Overhead Frame Position (RPOHFP[4:1]). RPOHFP[4:1] locates the individual PLCP path overhead bits in the receive overhead data stream, RPOH[4:1]. RPOHFP[4:1] is logic 1 while bit 1 (the most significant bit) of the path user channel octet (F1) is present in the RPOH[4:1] stream. RPOHFP[4:1] is updated on the falling edge of RPOHCLK[4:1]. RPOHFP[4:1] is available when the PLCPEN register bit is logic 1 in the SPLR Configuration Register.
REF8KO[4] REF8KO[3] REF8KO[2] REF8KO[1]
Output
U12 Y9 Y6 V4
RPOHFP[4] RPOHFP[3] RPOHFP[2] RPOHFP[1]
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name RFPO[4] RFPO[3] RFPO[2] RFPO[1]
Type Output
Pin No. U12 Y9 Y6 V4
Function Framer Receive Frame Pulse/Multi-frame Pulse (RFPO/RMFPO[4:1]). RFPO/RMFPO[4:1] is valid when the S/UNI-QJET is configured to be in framer only mode. The 8KREFO bit must be set to logic 0 S/UNI-QJET Configuration Register. RFPO[4:1] is aligned to RDATO[4:1] and indicates the position of the first bit in each DS3 M-subframe, the first bit in each G.751 E3 or G.832 E3 frame, or the first framing bit in each J2 frame
RMFPO[4] RMFPO[3] RMFPO[2] RMFPO[1]
RMFPO[4:1] is aligned to RDATO[4:1] and indicates the position of the first bit in each DS3 M-frame, the first bit in each G.751 or G.832 E3 multiframe, or the first framing bit in each J2 multiframe. RFPO/RMFPO[4:1] is updated on either the falling or rising edge of RSCLK[4:1] depending on the setting of the RSCLKR bit in the S/UNI-QJET Receive Configuration register.
RPOH[4] RPOH[3] RPOH[2] RPOH[1]
Output
V13 V10 U8 W4
Receive PLCP Overhead Data (RPOH[4:1]). RPOH[4:1] contains the PLCP path overhead octets (Zn, F1, B1, G1, M1, M2, and C1) extracted from the received PLCP frame when the PLCP layer is in-frame. When the PLCP layer is in the loss of frame state, RPOH[4:1] is forced to all ones. The octet data on RPOH[4:1] is shifted out in order from the most significant bit (bit 1) to the least significant bit (bit 8). RPOH[4:1] is updated on the falling edge of RPOHCLK[4:1].
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name ROVRHD[4] ROVRHD[3] ROVRHD[2] ROVRHD[1]
Type Output
Pin No. V13 V10 U8 W4
Function Framer Receive Overhead Indication (ROVRHD[4:1]). ROVRHD[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Registers. ROVRHD[4:1] will be high whenever the data on RDATO[4:1] corresponds to an overhead bit position. ROVRHD[4:1] is updated on the either the falling or rising edge of RSCLK[4:1] depending on the setting of the RSCLKR bit in the S/UNI-QJET Receive Configuration register. Receive PLCP Overhead Clock (RPOHCLK[4:1]). RPOHCLK[4:1] is active when PLCP processing is enabled. The frequency of this signal depends on the selected PLCP format. RPOHCLK[4:1] is nominally a 26.7 kHz clock for a DS1 PLCP frame, a 768 kHz clock for a DS3 PLCP frame, a 33.7 kHz clock for an E1 based PLCP frame, or a 576 kHz clock for a G.751 E3 based PLCP frame. RPOHFP[4:1] and RPOH[4:1] are updated on the falling edge of RPOHCLK[4:1]. Framer Recovered Clock (RSCLK[4:1]). RSCLK[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration Register. RSCLK[4:1] is the recovered clock and timing reference for RDATO[4:1], RFPO/RMFPO[4:1], and ROVRHD[4:1].
RPOHCLK[4] RPOHCLK[3] RPOHCLK[2] RPOHCLK[1]
Output
W13 U10 V7 U5
RSCLK[4] RSCLK[3] RSCLK[2] RSCLK[1]
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name RGAPCLK[4] RGAPCLK[3] RGAPCLK[2] RGAPCLK[1]
Type Output
Pin No. W13 U10 V7 U5
Function Framer Recovered Gapped Clock (RGAPCLK[4:1]). RGAPCLK[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Register and the RXGAPEN bit in the S/UNI-QJET Configuration 2 Register. RGAPCLK[4:1] is the recovered clock and timing reference for RDATO[4:1]. RGAPCLK[4:1] is held high for bit positions which correspond to overhead.
LCD[4] LCD[3] LCD[2] LCD[1]
Output
Y14 W10 W7 Y4
Loss of Cell Delineation (LCD[4:1]). LCD[4:1] is an active high signal which is asserted while the ATM cell processor has detected a Loss of Cell Delineation defect. The FRMRONLY bit in the S/UNI-QJET Configuration 1 Register must be set to logic 0 for LCD[4:1] to be valid. Framer Receive Data (RDATO[4:1]). RDATO[4:1] is valid when the S/UNI-QJET is configured as a DS3, E3, or J2 framer for non-ATM applications by setting the FRMRONLY bit in the S/UNI-QJET Configuration 1 Register. RDATO[4:1] is the received data aligned to RFPO/RMFPO[4:1] and ROVRHD[4:1]. RDATO[4:1] is updated on the active edge (as set by the RSCLKR register bit) of RSCLK[4:1] or RGAPCLK[4:1].
RDATO[4] RDATO[3] RDATO[2] RDATO[1]
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name FRMSTAT[4] FRMSTAT[3] FRMSTAT[2] FRMSTAT[1]
Type Output
Pin No. U1 U2 T4 U3
Function Framer Status (FRMSTAT[4:1]). FRMSTAT[4:1] is an active high signal which can be configured to show when one of the J2, E3, DS3, or PLCP framers have detected certain conditions. The FRMSTAT[4:1] outputs can be programmed via the STATSEL[2:0] bits in the S/UNI-QJET Configuration 2 Register to indicate: E3/DS3 Loss of Frame or J2 extended Loss of Frame, E3/DS3 Out of Frame or J2 Loss of Frame, PLCP Loss of Frame, PLCP Out of Frame, AIS, Loss of Signal, and DS3 Idle. FRMSTAT[4:1] should be treated as a glitch free asynchronous signal. ATM Interface Bus Width Selection (ATM8). The ATM8 input pin determines whether the S/UNI-QJET works with a 8bit wide interface (RDAT[7:0] and TDAT[7:0]) or a 16-bit wide interface (RDAT[15:0] and TDAT[15:0]). If ATM8 is set to logic 1, then the 8-bit wide interface is chosen. If ATM8 is set to logic 0, then the 16-bit wide interface is chosen.
ATM8
Input
L18
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0]
Type Input
Pin No. C15 A16 B16 D15 C16 A17 B17 D16 C17 D18 E17 D19 D20 E18 F17 E19
Function Transmit Cell Data Bus (TDAT[15:0]). This bus carries the ATM cell octets that are written to the selected transmit FIFO. TDAT[15:0] is sampled on the rising edge of TFCLK and is considered valid only when TENB is simultaneously asserted and the S/UNI-QJET has been selected via the TADR[4:2] and PHY_ADR[2:0] inputs. The S/UNI-QJET can be configured to operate with an 8-bit wide or 16-bit wide ATM data interface via the ATM8 input pin. When configured for the 8-bit wide interface, TDAT[15:8] are not used and should be tied to ground.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TPRTY
Type Input
Pin No. G19
Function Transmit bus parity (TPRTY). The transmit parity (TPRTY) signal indicates the parity of the TDAT[15:0] or TDAT[7:0] bus. If configured for the 8-bit bus (via the ATM8 input pin), then parity is calculated over TDAT[7:0]. If configured for the 16-bit bus, then parity is calculated over TDAT[15:0]. A parity error is indicated by a status bit and a maskable interrupt. Cells with parity errors are inserted in the transmit stream, so the TPRTY input may be unused. Odd or even parity selection is made using the TPTYP register bit. TPRTY is sampled on the rising edge of TFCLK and is considered valid only when TENB is simultaneously asserted and the S/UNI-QJET has been selected via the TADR[4:0] and PHY_ADR[2:0] inputs.
TSOC
Input
G20
Transmit Start of Cell (TSOC). The transmit start of cell (TSOC) signal marks the start of cell on the TDAT bus. When TSOC is high, the first word of the cell structure is present on the TDAT bus. It is not necessary for TSOC to be present for each cell. An interrupt may be generated if TSOC is high during any word other than the first word of the cell structure. TSOC is sampled on the rising edge of TFCLK and is considered valid only when TENB is simultaneously asserted and the S/UNI-QJET has been selected via the TADR[4:2] and PHY_ADR[2:0] inputs.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TENB
Type Input
Pin No. H18
Function Transmit Multi-Phy Write Enable (TENB). The TENB signal is an active low input which is used along with the TADR[4:0] inputs to initiate writes to the transmit FIFOs. When sampled low using the rising edge of TFCLK, the word on the TDAT bus is written into the transmit FIFO selected by the TADR[4:0] address bus. When sampled high using the rising edge of TFCLK, no write is performed, but the TADR[4:0] address is latched to identify the transmit FIFO to be accessed. A complete 53 octet cell must be written to the transmit FIFO before it is inserted into the transmit stream. Idle cells are inserted when a complete cell is not available. Transmit Address (TADR[4:0]). The TADR[4:0] bus is used to select the FIFO (and hence port) that is written to using the TENB signal and the FIFO whose cellavailable signal is visible on the TCA output. TADR[4:0] is sampled on the rising edge of TFCLK together with TENB. Note that the null-PHY address 1FH is an invalid address and will not be identified to any port on the S/UNI-QJET.
TADR[4] TADR[3] TADR[2] TADR[1] TADR[0]
Input
F18 F19 F20 G18 H17
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TCA
Type Output
Pin No. H19
Function Transmit Multi-Phy Cell Available (TCA). The TCA signal indicates when a cell is available in the transmit FIFO for the port selected by TADR[4:0]. When high, TCA indicates that the corresponding transmit FIFO is not full and a complete cell may be written. When TCA goes low, it can be configured to indicate either that the corresponding transmit FIFO is near full or that the corresponding transmit FIFO is full. TCA will transition low on the rising edge of TFCLK which samples Payload byte 43 (TCALEVEL0=0) or 47 (TCALEVEL0=1) for the 8-bit interface (ATM8=1), or the rising edge of TFCLK which samples Payload word 19 (TCALEVEL0=0) or 23 (TCALEVEL0=1) for the 16-bit interface (ATM8=0) if the PHY being polled is the same as the PHY in use. To reduce FIFO latency, the FIFO depth at which TCA indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level TCA is set to indicate "full" at, the transmit cell processor can store 4 complete cells. TCA is tri-stated when either the null-PHY address (1FH) or an address not matching the address space set by PHY_ADR[2:0] is latched (by TFCLK) from the TADR[4:2] inputs. The polarity of TCA (with respect the the description above) is inverted when the TCAINV register bit is set to logic 1.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name TFCLK
Type Input
Pin No. E20
Function Transmit FIFO Write Clock (TFCLK). This signal is used to write ATM cells to the four cell transmit FIFOs. TFCLK cycles at a 52 MHz or lower instantaneous rate. Please note that the TFCLK input is not 5 V tolerant, it is a 3.3 V only input pin.
DTCA[4] DTCA[3] DTCA[2] DTCA[1]
Output
J17 J18 J19 K19
Direct Access Transmit Cell Available (DTCA[4:1]). These output signals indicate when a cell is available in the transmit FIFO for the corresponding port. When high, DTCA[x] indicates that the corresponding transmit FIFO is not full and a complete cell may be written. DTCA[x] can be configured to indicate either that the corresponding transmit FIFO is near full and can accept no more than four writes or that the corresponding transmit FIFO is full. DTCA[x] will thus transition low on the rising edge of TFLCK which samples Payload byte 43 (TCALEVEL0=0) or 47 (TCALEVEL0=1) for the 8-bit interface (ATM8=1), or the rising edge of TFCLK which samples Payload word 19 (TCALEVEL0=0) or 23 (TCALEVEL0=1) for the 16-bit interface (ATM8=0). To reduce FIFO latency, the FIFO depth at which DTCA[x] indicates "full" can be set to one, two, three or four cells. Note that regardless of what fill level DTCA[x] is set to indicate "full" at, the transmit cell processor can store 4 complete cells. The polarity of DTCA[x] (with respect the the description above) is inverted when the TCAINV register bit is set to logic 1. The DTCA[4:1] outputs can be used to support Utopia Direct Access mode.
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Pin Name RDAT[15] RDAT[14] RDAT[13] RDAT[12] RDAT[11] RDAT[10] RDAT[9] RDAT[8] RDAT[7] RDAT[6] RDAT[5] RDAT[4] RDAT[3] RDAT[2] RDAT[1] RDAT[0] RPRTY
Type Output
Pin No. T20 T19 R17 T18 U20 U19 T17 U18 V17 U16 W17 Y17 V16 U15 W16 Y16
Function Receive Cell Data Bus (RDAT[15:0]). This bus carries the ATM cell octets that are read from the receive ATM FIFO selected by RADR[4:0]. RDAT[15:0] is tri-stated when RENB is high. RDAT[15:0] is updated on the rising edge of RFCLK. The S/UNI-QJET can be configured to operate with an 8-bit wide or 16-bit wide ATM data interface via the ATM8 input pin. RDAT[15:8] will remain tri-stated if ATM8 is set to logic 1. RDAT[15:0] is tri-stated when either the null-PHY address (1FH) or an address not matching the address space set by PHY_ADR[2:0] is latched from the RADR[4:2] inputs when RENB is high.
Output
R18
Receive Parity (RPRTY). The receive parity (RPRTY) signal indicates the parity of the RDAT bus. The S/UNI-QJET can be configured to operate with an 8-bit wide or 16-bit wide ATM data interface via the ATM8 input pin. In the 8-bit mode, RPRTY reflects the parity of RDAT[7:0]. In the 16-bit mode, RPRTY reflects the parity of RDAT[15:0]. Odd or even parity selection is made using the RXPTYP register bit. RPRTY is tri-stated when either the nullPHY address (1FH) or an address not matching the address space set by PHY_ADR[2:0] is latched from the RADR[4:2] inputs when RENB is high.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Pin Name RSOC
Type Output
Pin No. M17
Function Receive Start of Cell (RSOC). This signal marks the start of cell on the RDAT bus. RSOC marks the start of the cell on the RDAT bus. RSOC is tri-stated when either the nullPHY address (1FH) or an address not matching the address space set by PHY_ADR[2:0] is latched from the RADR[4:0] inputs when RENB is high.
RENB
Input
N18
Receive Multi-Phy Read Enable (RENB). The RENB signal is used to initiate reads from the receive FIFOs. When sampled low using the rising edge of RFCLK, a byte is read (if one is available) from the receive FIFO selected by the RADR[4:0] address bus and output on the RDAT bus. When sampled high using the rising edge of RFCLK, no read is performed and RDAT[15:0], RPRTY, and RSOC are tristated, and the address on RADR[4:0] is latched to select the device or port for the next ATM FIFO access. RENB must operate in conjunction with RFCLK to access the FIFOs at a high enough rate to prevent FIFO overflows. The ATM layer device may de-assert RENB at anytime it is unable to accept another byte.
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Pin Name RADR[4] RADR[3] RADR[2] RADR[1] RADR[0]
Type Input
Pin No. P19 N17 P18 R20 R19
Function Receive Address (RADR[4:0]). The RADR[4:1] signal is used to select the FIFO (and hence port) that is read from using the RENB signal and the FIFO whose cell-available signal is visible on the RCA output. RADR[4:0] is sampled on the rising edge of RFCLK together with RENB. Note that the null-PHY address 1FH is an invalid address and will not be identified to any port on the S/UNI-QJET.
RCA
Output
N19
Receive Multi-Phy Cell Available (RCA). The RCA signal indicates when a cell is available in the receive FIFO for the port selected by RADR[4:0]. RCA can be configured to be de-asserted when either zero or four bytes remain in the selected/addressed FIFO. RCA will thus transition low on the rising edge of RFCLK after Payload byte 48 (RCALEVEL0=1) or 43 (RCALEVEL0=0) is output for the 8-bit interface (ATM8=1), or after Payload word 24 (RCALEVEL0=1) or 19 (RCALEVEL0=0) is output for the 16-bit interface (ATM8=0) if the PHY being polled is the same as the PHY in use. RCA is tri-stated when either the null-PHY address (1FH) or an address not matching the address space set by PHY_ADR[2:0] is latched (by RFCLK) from the RADR[4:2] inputs. The polarity of RCA (with respect to the description above) is inverted when the RCAINV register bit is set to logic 1.
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Pin Name RFCLK
Type Input
Pin No. P20
Function Receive FIFO Read Clock (RFCLK). This signal is used to read ATM cells from the receive FIFOs. RFCLK must cycle at a 52 MHz or lower instantaneous rate, but at a high enough rate to avoid FIFO overflows. Please note that the RFCLK input is not 5 V tolerant, it is a 3.3 V only input pin.
DRCA[4] DRCA[3] DRCA[2] DRCA[1]
Output
L17 M20 M19 M18
Direct Access Receive Cell Available (DRCA[4:1]). These output signals indicate when a cell is available in the receive FIFO for the corresponding port. DRCA[4:1] can be configured to be deasserted when either zero or four bytes remain in the FIFO. DRCA[4:1] will thus transition low on the rising edge of RFCLK after Payload byte 48 (RCALEVEL0=1) or 43 (RCALEVEL0=0) is output for the 8-bit interface (ATM8=1), or after Payload word 24 (RCALEVEL0=1) or 19 (RCALEVEL0=0) is output for the 16-bit interface (ATM8=0). The DRCA[4:1] outputs can be used to support Utopia Direct Access mode.
PHY_ADR[2] PHY_ADR[1] PHY_ADR[0]
Input
K18 L20 L19
Device Identification Address (PHY_ADR[2:0]). The PHY_ADR[2:0] inputs are the most-significant bits of the address space which this S/UNI-QJET occupies. When the PHY_ADR[2:0] inputs match the TADR[4:2] or RADR[4:2] inputs, then one of the four quadrants (as determined by the TADR[1:0] or RADR[1:0] inputs) in this S/UNI-QJET is selected for transmit or receive ATM access. Note that the null-PHY address 1FH is an invalid address and will not be identified to any port on the S/UNI-QJET.
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Pin Name CSB
Type Input
Pin No. C9
Function Active low Chip Select (CSB). This signal must be low to enable S/UNI-QJET register accesses. If CSB is not used, (RDB and WRB determine register reads and writes) then it should be tied to an inverted version of RSTB. Active low Write Strobe (WRB). This signal is pulsed low to enable a S/UNI-QJET register write access. The D[7:0] bus is clocked into the addressed register on the rising edge of WRB while CSB is low. Active low Read Enable (RDB). This signal is pulsed low to enable a S/UNI-QJET register read access. The S/UNI-QJET drives the D[7:0] bus with the contents of the addressed register while RDB and CSB are both low. Bi-directional Data Bus (D[7:0]). The bidirectional data bus D[7:0] is used during S/UNI-QJET register read and write accesses.
WRB
Input
B8
RDB
Input
D9
D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0]
I/O
D12 C13 A14 B14 D13 C14 A15 B15
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Pin Name A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] A[0] RSTB
Type Input
Pin No. B9 B10 C10 A11 B11 C11 D11 A12 B12 C12 B13
Function Address Bus (A[10:0]). The address bus A[10:0] selects specific registers during S/UNI-QJET register accesses.
Input
C8
Active low Reset (RSTB). This signal is set low to asynchronously reset the S/UNI-QJET. RSTB is a Schmitt-trigger input with an integral pull-up resistor. Address Latch Enable (ALE). The address latch enable (ALE) is active-high and latches the address bus A[10:0] when low. When ALE is high, the internal address latches are transparent. It allows the S/UNI-QJET to interface to a multiplexed address/data bus. ALE has an integral pull-up resistor. Active low Open-Drain Interrupt (INTB). This signal goes low when an unmasked interrupt event is detected on any of the internal interrupt sources. Note that INTB will remain low until all active, unmasked interrupt sources are acknowledged at their source. Test Clock (TCK). This signal provides timing for test operations that can be carried out using the IEEE P1149.1 test access port.
ALE
Input
A8
INTB
Output
A7
TCK
Input
B6
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Pin Name TMS
Type Input
Pin No. C7
Function Test Mode Select (TMS). This signal controls the test operations that can be carried out using the IEEE P1149.1 test access port. TMS is sampled on the rising edge of TCK. TMS has an integral pull up resistor. Test Data Input (TDI). This signal carries test data into the S/UNI-QJET via the IEEE P1149.1 test access port. TDI is sampled on the rising edge of TCK. TDI has an integral pull up resistor. Test Data Output (TDO). This signal carries test data out of the S/UNI-QJET via the IEEE P1149.1 test access port. TDO is updated on the falling edge of TCK. TDO is a tri-state output which is inactive except when scanning of data is in progress. Active low Test Reset (TRSTB). This signal provides an asynchronous S/UNI-QJET test access port reset via the IEEE P1149.1 test access port. TRSTB is a Schmitt triggered input with an integral pull up resistor. TRSTB must be asserted during the power up sequence. Note that if not used, TRSTB must be connected to the RSTB input.
TDI
Input
D8
TDO
Output
B7
TRSTB
Input
A6
BIAS
Input
H20 U17 D4 U4
+5V Bias (BIAS). When tied to +5V, the BIAS input is used to bias the wells in the input and I/O pads so that the pads can tolerate 5V on their inputs without forward biasing internal ESD protection devices. When tied to VDD, the inputs and bidirectional inputs will only tolerate input levels up to VDD.
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Pin Name VDD[1] VDD[2] VDD[3] VDD[4] VDD[5] VDD[6] VDD[7] VDD[8] VDD[9] VDD[10] VDD[11] VDD[12] VDD[13] VDD[14] VDD[15] VDD[16] VDD[17] VDD[18] VDD[19] VDD[20] VDD[21] VDD[22] VDD[23] VDD[24] VDD[25] VDD[26] VDD[27] VDD[28]
Type Power
Pin No. B2 B3 B18 B19 C2 C3 C18 C19 D7 D10 D14 G4 G17 K17 L4 P4 P17 U7 U11 U14 V2 V3 V18 V19 W2 W3 W18 W19
Function DC Power. The DC Power pins should be connected to a well-decoupled +3.3V DC supply.
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Pin Name VSS[1] VSS[2] VSS[3] VSS[4] VSS[5] VSS[6] VSS[7] VSS[8] VSS[9] VSS[10] VSS[11] VSS[12] VSS[13] VSS[14] VSS[15] VSS[16] VSS[17] VSS[18] VSS[19] VSS[20] VSS[21] VSS[22] VSS[23] VSS[24] VSS[25] VSS[26] VSS[27] VSS[28] VSS[29]
Type Ground
Pin No. A1 A2 A3 A9 A10 A13 A18 A19 A20 B1 B20 C1 C20 H1 J20 K20 L1 M1 N20 V1 V20 W1 W20 Y1 Y2 Y3 Y8 Y11 Y12
Function DC Ground. The DC Ground pins should be connected to GND.
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Pin Name VSS[30] VSS[31] VSS[32]
Type Ground
Pin No. Y18 Y19 Y20
Function DC Ground. The DC Ground pins should be connected to GND.
Notes on Pin Description: 1. All S/UNI-QJET inputs and bi-directionals present minimum capacitive loading and operate at TTL logic levels. 2. All S/UNI-QJET outputs and bi-directionals have at least 3 mA drive capability. The data bus outputs, D[7:0], have 3 mA drive capability. The FIFO interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA, and DTCA[4:1], have 12 mA drive capability. The outputs TCLK[4:1], TPOS/TDATO[4:1], TNEG/TOHM[4:1], TPOHFP/TFPO/TMFPO/TGAPCLK[4:1], LCD/RDATO[4:1], RPOH/ROVRHD[4:1], RPOHCLK/RSCLK/RGAPCLK[4:1], and REF8KO/RPOHFP/RFPO/RMFPO[4:1] have 6 mA drive capability. All other outputs have 3 mA drive capability. 3. Inputs RSTB, ALE, TMS, TDI and TRSTB have internal pull-up resistors. 4. RSTB, TRSTB, TMS, TDI, TCK, REF8KI, TFCLK, RFCLK, TICLK[4:1], and RCLK[4:1] are schmitt trigger input pads. 5. RFCLK and TFCLK are 3.3 V only input pins - they are not 5 V tolerant. Connecting a 5 V signal to these inputs may result in damage to the part. 6. The VSS [32:1] ground pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the S/UNI-QJET. 7. The VDD[28:1] power pins are not internally connected together. Failure to connect these pins externally may cause malfunction or damage the device. These power supply connections must all be utilized and must all connect to a common +3.3 V or ground rail, as appropriate. 8. During power-up and power-down, the voltage on the BIAS pin must be kept equal to or greater than the voltage on the VDD [28:1] pins, to avoid damage to the device.
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9 9.1
FUNCTIONAL DESCRIPTION DS3 Framer The DS3 Framer (T3-FRMR) Block integrates circuitry required for decoding a B3ZS-encoded signal and framing to the resulting DS3 bit stream. The T3-FRMR is directly compatible with the M23 and C-bit parity DS3 applications. The T3-FRMR decodes a B3ZS-encoded signal and provides indications of line code violations. The B3ZS decoding algorithm and the LCV definition can be independently chosen through software. A loss of signal (LOS) defect is also detected for B3ZS encoded streams. LOS is declared when inputs RPOS and RNEG contain zeros for 175 consecutive RCLK cycles. LOS is removed when the ones density on RPOS and/or RNEG is greater than 33% for 175 1 RCLK cycles. The framing algorithm examines five F-bit candidates simultaneously. When at least one discrepancy has occurred in each candidate, the algorithm examines the next set of five candidates. When a single F-bit candidate remains in a set, the first bit in the supposed M-subframe is examined for the M-frame alignment signal (i.e., the M-bits, M1, M2, and M3 are following the 010 pattern). Framing is declared, and out-of-frame is removed, if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. During the examination of the M-bits, the X-bits and P-bits are ignored. The algorithm gives a maximum average reframe time of 1.5 ms. While the T3-FRMR is synchronized to the DS3 M-frame, the F-bit and M-bit positions in the DS3 stream are examined. An out-of-frame defect is detected when 3 F-bit errors out of 8 or 16 consecutive F-bits are observed (as selected by the M3O8 bit in the DS3 FRMR Configuration Register), or when one or more M-bit errors are detected in 3 out of 4 consecutive M-frames. The M-bit error criteria for OOF can be disabled by the MBDIS bit in the DS3 Framer Configuration register. The 3 out of 8 consecutive F-bits out-of-frame ratio provides more robust operation, in the presence of a high bit error rate, than the 3 out of 16 consecutive F-bits ratio. Either out-of-frame criteria allows an out-offrame defect to be detected quickly when the M-subframe alignment patterns or, optionally, when the M-frame alignment pattern is lost. Also while in-frame, line code violations, M-bit or F-bit framing bit errors, and Pbit parity errors are indicated. When C-bit parity mode is enabled, both C-bit parity errors and far end block errors are indicated. These error indications, as well as the line code violation and excessive zeros indication, are accumulated
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over 1 second intervals with the Performance Monitor (PMON). Note that the framer is an off-line framer, indicating both OOF and COFA events. Even if an OOF is indicated, the framer will continue indicating performance monitoring information based on the previous frame alignment. Three DS3 maintenance signals (a RED alarm condition, the alarm indication signal, and the idle signal) are detected by the T3-FRMR. The maintenance detection algorithm employs a simple integrator with a 1:1 slope that is based on the occurrence of "valid" M-frame intervals. For the RED alarm, an M-frame is said to be a "valid" interval if it contains a RED defect, defined as an occurrence of an OOF or LOS event during that M-frame. For AIS and IDLE, an M-frame interval is "valid" if it contains AIS or IDLE, defined as the occurrence of less than 15 discrepancies in the expected signal pattern (1010... for AIS, 1100... for IDLE) while valid frame alignment is maintained. This discrepancy threshold ensures the detection algorithms operate in the presence of a 10-3 bit error rate. For AIS, the expected pattern may be selected to be: the framed "1010" signal; the framed arbitrary DS3 signal and the C-bits all zero; the framed "1010" signal and the Cbits all zero; the framed all-ones signal (with overhead bits ignored); or the unframed all-ones signal (with overhead bits equal to ones). Each "valid" Mframe causes an associated integration counter to increment; "invalid" M-frames cause a decrement. With the "slow" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 127, which results in a detection time of 13.5 ms. With the "fast" detection option, RED, AIS, or IDLE are declared when the respective counter saturates at 21, which results in a detection time of 2.23 ms (i.e., 1.5 times the maximum average reframe time). RED, AIS, or IDLE are removed when the respective counter decrements to 0. DS3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted. Valid X-bits are extracted by the T3-FRMR to provide indication of far end receive failure (FERF). A FERF defect is detected if the extracted X-bits are equal and are logic 0 (X1=X2=0); the defect is removed if the extracted X-bits are equal and are logic 1 (X1=X2=1). If the X-bits are not equal, the FERF status remains in its previous state. The extracted FERF status is buffered for 2 M-frames before being reported within the DS3 FRMR Status register. This buffer ensures a better than 99.99% chance of freezing the FERF status on a correct value during the occurrence of an out of frame.
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When the C-bit parity application is enabled, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. Codes in the FEAC channel are detected by the Bit Oriented Code Detector (RBOC). HDLC messages in the Path Maintenance Data Link are received by the Data Link Receiver (RDLC). The T3-FRMR can be enabled to automatically assert the RAI indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or RED, or AIS. The T3-FRMR can also be enabled to automatically insert C-bit Parity FEBE upon detection of receive C-bit parity error. The T3-FRMR extracts the entire DS3 overhead (56 bits per M-frame) using the ROH output, along with the ROHCLK, and ROHFP outputs. The T3-FRMR may be configured to generate interrupts on error events or status changes. All sources of interrupts can be masked or acknowledged via internal registers. Internal registers are also used to configure the T3-FRMR. Access to these registers is via a generic microprocessor bus. 9.2 E3 Framer The E3 Framer (E3-FRMR) Block integrates circuitry required for decoding an HDB3-encoded signal and framing to the resulting E3 bit stream. The E3-FRMR is directly compatible with the G.751 and G.832 E3 applications. The E3-FRMR searches for frame alignment in the incoming serial stream based on either the G.751 or G.832 formats. For the G.751 format, the E3-FRMR expects to see the selected framing pattern error-free for three consecutive frames before declaring INFRAME. For the G.832 format, the E3-FRMR expects to see the selected framing pattern error-free for two consecutive frames before declaring INFRAME. Once the frame alignment is established, the incoming data is continuously monitored for framing bit errors and byte interleaved parity errors (in G.832 format). While in-frame, the E3-FRMR also extracts various overhead bytes and processes them according to the framing format selected: In G.832 E3 format, the E3-FRMR extracts: * the Trail Trace bytes and outputs them as a serial stream for further processing by the Trail Trace Buffer (TTB) block;
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*
the FERF bit and indicates an alarm when the FERF bit is a logic 1 for 3 or 5 consecutive frames. The FERF indication is removed when the FERF bit is a logic 0 for 3 or 5 consecutive frames; the FEBE bit and outputs it for accumulation in PMON; the Payload Type bits and buffers them so that they can be read by the microprocessor; the Timing Marker bit and asserts the Timing Marker indication when the value of the extracted bit has been in the same state for 3 or 5 consecutive frames; the Network Operator byte and presents it as a serial stream for further processing by the RDLC block when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 1. The byte is also brought out on the ROH[x] output with an associated clock on ROHCLK[x]. All 8 bits of the Network Operator byte are extracted and presented on the overhead output and, optionally, presented to the RDLC. the General Purpose Communication Channel byte and presents it to the RDLC when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0 The byte is also brought out on the ROH[x] output with an associated clock on ROHCLK[x].
* * *
*
*
In G.751 E3 mode, the E3-FRMR extracts: * the Remote Alarm Indication bit (bit 11 of the frame) and indicates a Remote Alarm when the RAI bit is a logic 1 for 3 or 5 consecutive frames. Similarly, the Remote Alarm is removed when the RAI bit is logic 0 for 3 or 5 consecutive frames; the National Use reserved bit (bit 12 of the frame) and presents it as a serial stream for further processing in the RDLC when the RNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0. The bit is also brought out on the ROH[x] output with an associated clock on ROHCLK[x]. Optionally, an interrupt can be generated when the National Use bit changes state.
*
Further, while in-frame, the E3-FRMR indicates the position of all the overhead bits in the incoming digital stream to the ATMF/SPLR block. For G.751 mode, the tributary justification bits can optionally be identified as either overhead or payload for payload mappings that take advantage of the full bandwidth.
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The E3-FRMR declares out of frame alignment if the framing pattern is in error for four consecutive frames. The E3-FRMR is an "off-line" framer, where all frame alignment indications, all overhead bit indications, and all overhead bit processing continue based on the previous alignment. Once the framer has determined the new frame alignment, the out-of-frame indication is removed and a COFA indication is declared if the new alignment differs from the previous alignment. The E3-FRMR detects the presence of AIS in the incoming data stream when less than 8 zeros in a frame are detected while the framer is OOF in G.832 mode, or when less than 5 zeros in a frame are detected while OOF in G.751 mode. This algorithm provides a probability of detecting AIS in the presence of a 10-3 BER as 92.9% in G.832 and 98.0% in G.751. Loss of signal is LOS is declared when no marks have been received for 32 consecutive bit periods. Loss of signal is de-asserted after 32 bit periods during which there is no sequence of four consecutive zeros. E3 Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer de-asserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted. The E3-FRMR can also be enabled to automatically assert the RAI/FERF indication in the outgoing transmit stream upon detection of any combination of LOS, OOF or AIS. The E3-FRMR can also be enabled to automatically insert G.832 FEBE upon detection of receive BIP-8 errors. 9.3 J2 Framer The J2-FRMR integrates circuitry to decode a unipolar or B8ZS encoded signal and frame to the resulting 6312 kbps J2 bit stream. Having found frame, the J2FRMR extracts a variety of overhead and datalink information from the J2 bit stream. The J2 format consists of 789-bit frames, each 125s long, consisting of 96 bytes of payload, 2 reserved bytes, and 5 F-bits. The frames are grouped into 4frame multiframes. The multiframe format is as follows:
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Bit # Frm. 1 Frm. 2 Frm. 3 Frm. 4
1-8 TS1[1:8] TS1[1:8] TS1[1:8] TS1[1:8]
... ... ... ... ...
761-768 TS96[1:8] TS96[1:8] TS96[1:8] TS96[1:8]
769-776 TS97[1:8] TS97[1:8] TS97[1:8] TS97[1:8]
777-784 TS98[1:8] TS98[1:8] TS98[1:8] TS98[1:8]
785 1 1 x1 e1
786 1 0 x2 e2
787 0 1 x3 e3
788 0 0 a e4
789 m 0 m e5
TS1 .. TS96 : TS97, TS98:
Byte interleaved payload Reserved channels for signaling represented as binary ones and zeroes
Frame Alignment Signal: m: x1, x2, x3: a: e1..e5:
4-kHz datalink Spare bits, usually logic 1 Remote Loss of Frame alarm bit, active high CRC-5 check sequence. The entire 3156-bit multiframe, including the CRC-5 check sequence, should have a remainder of 0 when divided by x5 + x4 + x2 + 1
The J2-FRMR frames to a J2 signal with an average reframe time of 5.07 ms. An alternate framing algorithm that uses the CRC-5 check to detect static mimic patterns is available. Once in frame, the J2-FRMR provides indications of frame and multiframe boundaries, and marks overhead bits, x-bits, m-bits, and reserved channels (TS97 and TS98). Indications of loss of signal, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and CRC errors are provided, and may be accumulated by the PMON (with the exception of change of frame alignment); maskable interrupts are available to alert the microprocessor to the occurrence of any of these events. In addition to marking x-bit values, J2-FRMR provides microprocessor access to the x-bits, and will optionally generate an interrupt when any of the x-bits changes state. The m-bits and the associated clock are can either be extracted through the RDLC or through the ROH[x] and ROHCLK[x] output pins of the S/UNI-QJET. The m-bits are also presented to the RBOC for detection of any generic bit-oriented codes. Status signals such as Physical AIS, Payload AIS, Remote Alarm Indication in
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m-bits, and Remote Loss of Frame (a-bit) are detected by the J2-FRMR. In addition to providing indication signals of these states, the J2-FRMR will optionally generate an interrupt when any of these status signals changes. J2 LOS is declared when no marks have been received for one of 15, 31, 63, or 255 consecutive bit periods. J2 LOS is cleared when either 15, 31, 63, or 255 consecutive bit periods have passed without an excessive zeros (8 or more consecutive zeros) detection as required by ITU-T G.775. J2 LOF is declared when 7 or more consecutive multiframes with errored framing patterns are received. The J2 LOF is cleared when 3 or more consecutive multiframes with correct framing patterns are received. A framing algorithm which takes into account the CRC calculation is also available. The framing algorithms are described in the following text. J2 Physical Layer AIS is declared when 2 or less zeros are detected in a sequence of 3156 bits. It is cleared when 3 or more zeros is detected in a sequence of 3156 bits as required by ITU-T G.775. J2 Payload AIS is detected when the incoming J2 payload has 2 or less zeros in a sequence of 3072 bits. It is cleared when 3 or more zeros are detected in a sequence of 3072 bits. The J2-FRMR may be forced to re-frame by microprocessor control. Similarly, the microprocessor may disable the J2-FRMR from reframing due to framing bit errors. The J2-FRMR may be configured, and all sources of interrupts may be masked or acknowledged, via internal registers. These internal registers are accessed via a generic microprocessor bus. 9.3.1 J2 Frame Find Algorithms The J2-FRMR searches for frame alignment using one of two algorithms, as selected by the CRC_REFR bit in the J2-FRMR Configuration Register. When the CRC_REFR bit is set to logic 0, the J2-FRMR uses only the frame alignment sequence to find frame, searching for three consecutive correct frame alignment sequences. The frame find block searches for the entire 9-bit sequence (spread over two multiframes) at the same time, greatly reducing the time required to find frame alignment. The framing process with CRC-REFR cleared is illustrated in Figure 8.
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Figure 8
- Framing algorithm (CRC_REFR = 0)
R es et or O ut of Fram e
S lip 1 bit
Fram ing Pattern Matched Mark multiframe alignment
E lse
Fail
C onfirm Fram ing Pattern in next m ultifra m e
P a ss Fail
C onfirm F ram ing Pattern in next m ultifram e
P a ss
Declare in-frame
Using this algorithm, the J2-FRMR will on average find frame in 5.07ms when starting the search in the worst possible position, given a 10 -4 error rate and no static mimic patterns. When the CRC_REFR bit is set to logic 1, in addition to requiring three consecutive correct framing patterns, the J2-FRMR requires that the first two CRC-5 checks be correct, or a reframe is initiated. To speed the process, the CRC-5 and frame alignment checks are run concurrently, as illustrated in Figure 9.
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Figure 9
- Framing Algorithm (CRC_REFR = 1)
R eset or O ut o f Fram e
S lip 1 bit
Fram ing Pattern Matc hed Mark multiframe alignment
E lse
Fail
C onfirm F ram ing Pattern in next m ultifram e
P a ss Fail
C hec k C R C -5 Sequence
P a ss Fail
C onfirm F ram ing Pattern in next m ultifram e
P a ss Fail
C hec k C R C -5 Sequenc e
P a ss
Declare in-frame
Using this algorithm, the J2-FRMR will find frame in 10.22ms, on average when starting the search in the worst possible position, given a 10 -4 error rate and no static mimic patterns. The algorithm will reject 99.90% of mimic patterns. Further protection against mimic patterns is available by monitoring the rate of CRC-5 errors. Once frame alignment is found, the block sets the LOF indication low, indicates a change of frame alignment (if it occurred). The block declares loss of frame alignment if 7 consecutive FASs have been received in error. In the presence of a random 10-3 bit error rate the frame loss criteria provides a mean time to falsely lose frame alignment of 1.65 years. The Frame Find Block can be forced to initiate a frame search at any time when the REFRAME bit in the J2-FRMR Configuration. Conversely, when the FLOCK bit is set to logic 1, the J2-FRMR
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will never declare Loss of Frame or search for a new frame alignment due to excess framing bit errors. J2 extended Loss of Frame detection is provided as recommended by ITU-T G.783 with programmable integration periods of 1ms, 2ms, or 3ms. While integrating up to assert LOF, the counter will integrate up when the framer asserts an Out of Frame condition and integrates down when the framer deasserts the Out of Frame condition. Once an LOF is asserted, the framer must not assert OOF for the entire integration period before LOF is de-asserted. 9.4 PMON Performance Monitor Accumulator The Performance Monitor (PMON) Block interfaces directly with either the DS3 Framer (T3-FRMR) to accumulate line code violation (LCV) events, parity error (PERR) events, path parity error (CPERR) events, far end block error (FEBE) events, excess zeros (EXZS), and framing bit error (FERR) events using saturating counters; the E3 Framer (E3-FRMR) to accumulate LCV, PERR (in G.832 mode), FEBE and FERR events; or the J2 Framer (J2-FRMR) to accumulate LCVs, CRC errors (in the PERR counter), Framing bit errors (FERR), and excess zeros (EXZS). The PMON stops accumulating error signal from the E3, DS3, or J2 Framers once frame synchronization is lost. When an accumulation interval is signaled by a write to the PMON register address space or a write to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register, the PMON transfers the current counter values into microprocessor accessible holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed. When counter data is transferred into the holding registers, an interrupt is generated, providing the interrupt is enabled. If the holding registers have not been read since the last interrupt, an overrun status bit is set. In addition, a register is provided to indicate changes in the PMON counters since the last accumulation interval. 9.5 RBOC Bit-Oriented Code Detector The Bit-Oriented Code Detector is only used in DS3 C-bit Parity or J2 mode. The Bit-Oriented Code Detector (RBOC) Block detects the presence of 63 of the 64 possible bit-oriented codes (BOCs) contained in the DS3 C-bit parity far-end alarm and control (FEAC) channel or in the J2 datalink signal stream. The 64th code ("111111") is similar to the HDLC flag sequence and is ignored.
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Bit-oriented codes (BOCs) are received on the FEAC channel as 16-bit sequences each consisting of 8 ones, a zero, 6 code bits, and a trailing zero ("111111110xxxxxx0"). BOCs are validated when repeated at least 10 times. The RBOC can be enabled to declare a code valid if it has been observed for 8 out of 10 times or for 4 out of 5 times, as specified by the AVC bit in the RBOC Configuration/Interrupt Enable Register. The RBOC declares that the code is removed if two code sequences containing code values different from the detected code are received in a moving window of ten code periods. Valid BOCs are indicated through the RBOC Interrupt Status Register. The BOC bits are set to all ones ("111111") when no valid code is detected. The RBOC can be programmed to generate an interrupt when a detected code has been validated and when the code is removed. 9.6 RDLC Facility Data Link Receiver The RDLC is a microprocessor peripheral used to receive LAPD/HDLC frames on any serial HDLC bit stream that provides data and clock information such as the DS3 C-bit parity Path Maintenance Data Link, the E3 G.832 Network Requirement byte or the General Purpose data link (selectable using the RNETOP bit in the S/UNI-QJET Data Link and FERF/RAI Control register), the E3 G.751 Network Use bit, or the J2 m-bit Data Link. The RDLC detects the change from flag characters to the first byte of data, removes stuffed zeros on the incoming data stream, receives packet data, and calculates the CRC-CCITT frame check sequence (FCS). In the address matching mode, only those packets whose first data byte matches one of two programmable bytes or the universal address (all ones) are stored in the FIFO. The two least significant bits of the address comparison can be masked for LAPD SAPI matching. Received data is placed into a 128-level FIFO buffer. An interrupt is generated when a programmable number of bytes are stored in the FIFO buffer. Other sources of interrupt are detection of the terminating flag sequence, abort sequence, or FIFO buffer overrun. The Status Register contains bits which indicate the overrun or empty FIFO status, the interrupt status, and the occurrence of first flag or end of message bytes written into the FIFO. The Status Register also indicates the abort, flag, and end of message status of the data just read from the FIFO. On end of message, the Status Register indicates the FCS status and if the packet contained a non-integer number of bytes.
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9.7
SPLR PLCP Layer Receiver The PLCP Layer Receiver (SPLR) Block integrates circuitry to support DS1, DS3, E1, and G.751 E3 PLCP frame processing. The SPLR provides framing for PLCP based transmission formats. The SPLR frames to DS1, DS3, E1, and G.751 E3 based PLCP frames with maximum average reframe times of 635 s, 22 s, 483 s, and 32 s respectively. Framing is declared (out of frame is removed) upon finding 2 valid, consecutive sets of framing (A1 and A2) octets and 2 valid and sequential path overhead identifier (POHID) octets. While framed, the A1, A2, and POHID octets are examined. OOF is declared when an error is detected in both the A1 and A2 octets or when 2 consecutive POHID octets are found in error. LOF is declared when an OOF state persists for more than 25 ms, 1 ms, 20 ms, or 1 ms for DS1, DS3, E1, or G.751 E3 PLCP formats respectively. If the OOF events are intermittent, the LOF counter is decremented at a rate 1/12 (DS3 PLCP), 1/10 (E1, DS1 PLCP) or 1/9(G.751 E3 PLCP) of the incrementing rate. LOF is thus removed when an in-frame state persists for more than 250 ms for a DS1 signal, 12 ms for a DS3 signal, 200 ms for an E1 signal, or 9 ms for a G.751 E3 signal. When LOF is declared, PLCP reframe is initiated. When in frame, the SPLR extracts the path overhead octets and outputs them bit serially on output RPOH, along with the RPOHCLK and RPOHFP outputs. Framing octet errors and path overhead identifier octet errors are indicated as frame errors. Bit interleaved parity errors and far end block errors are indicated. The yellow signal bit is extracted and accumulated to indicate yellow alarms. Yellow alarm is declared when 10 consecutive yellow signal bits are set to logical 1; it is removed when 10 consecutive received yellow signal bits are set to logical 0. The C1 octet is examined to maintain nibble alignment with the incoming transmission system sublayer bit stream.
9.8
ATMF ATM Cell Delineator The ATM Cell Delineator (ATMF) Block integrates circuitry to support HCS-based cell delineation for non-PLCP based transmission formats. The ATMF block accepts a bit serial cell stream from an upstream transmission system sublayer entity (such as the T3-FRMR, E3-FRMR, or J2-FRMR Block) and performs cell delineation to locate the cell boundaries. For PLCP applications, ATM cell positions are fixed relative to the PLCP frame, but the ATMF still performs cell delineation to locate the cell boundaries. Cell delineation is the process of framing to ATM cell boundaries using the header check sequence (HCS) field found in the ATM cell header. The HCS is a
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CRC-8 calculation over the first 4 octets of the ATM cell header. When performing delineation, correct HCS calculations are assumed to indicate cell boundaries. The ATMF performs a sequential bit-by-bit, a nibble-by-nibble (DS-3 direct mapped), or a byte-by-byte (J2 and E3 direct-mapped) hunt for a correct HCS sequence. This state is referred to as the HUNT state. When receiving a bit serial cell stream from an upstream transmission system sublayer entity, the bit, nibble, or byte boundaries are determined from the location of the overhead. When a correct HCS is found, the ATMF locks on the particular cell boundary and assumes the PRESYNC state. This state verifies that the previously detected HCS pattern was not a false indication. If the HCS pattern was a false indication then an incorrect HCS should be received within the next DELTA cells. At that point a transition back to the HUNT state is executed. If an incorrect HCS is not found in this PRESYNC period then a transition to the SYNC state is made. In this state synchronization is not relinquished until ALPHA consecutive incorrect HCS patterns are found. In such an event a transition is made back to the HUNT state. The state diagram of the cell delineation process is shown in Figure 10. Figure 10 - Cell delineation State Diagram
C o rrec t H C S (b it b y b it)
HU NT In c o rr ec t H C S (c ell b y ce ll)
PRESYNC
A L P H A c o n s ec u tive in c o rrec t H C S 's (c ell b y ce ll) SYNC
D E L T A c o n se c u tiv e co r rec t H C S 's (c ell b y ce ll)
The values of ALPHA and DELTA determine the robustness of the delineation method. ALPHA determines the robustness against false misalignments due to bit errors. DELTA determines the robustness against false delineation in the
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synchronization process. ALPHA is chosen to be 7 and DELTA is chosen to be 6 as recommended in ITU-T Recommendation I.432. These values result in a maximum average time to frame of 127 s for a DS3 stream carrying ATM cells directly mapped into the DS3 information payload. Loss of cell delineation (LCD) is detected by counting the number of incorrect cells while in the HUNT state. The counter value is stored in the RXCP-50 LCD Count Threshold register. The threshold has a default value of 360 which results in a DS3 application detection time of 3.5 ms, an E3 G.832 application detection time of 4.5 ms, and E3 G.751 application detection time of 5.0 ms, a J2 application time of 24.8ms, an E1 application detection time of 77 ms, and a DS1 application detection time of 100 ms. If the counter value is set to zero, the LCD output signal is asserted for every incorrect cell. 9.9 RXCP-50 Receive Cell Processor The Receive Cell Processor (RXCP-50) Block integrates circuitry to support scrambled or unscrambled cell payloads, scrambled or unscrambled cell headers, header check sequence (HCS) verification, idle cell filtering, and performance monitoring. The RXCP-50 operates upon a delineated cell stream. For PLCP based transmissions systems, cell delineation is performed by the SPLR. For nonPLCP based transmission systems, cell delineation is performed by the ATMF. Framing status indications from these blocks ensure that cells are not written to the RXFF while the SPLR is in the loss of frame state, or cells are not written to the RXFF while the ATMF is in the HUNT or PRESYNC states. The RXCP-50 descrambles the cell payload field using the self synchronizing descrambler with a polynomial of x43 + 1. The header portion of the cells can optionally be descrambled also. Note that cell payload scrambling is enabled by default in the S/UNI-QJET as required by ITU-T Recommendation I.432, but may be disabled to ensure backwards compatibility with older equipment. The HCS is a CRC-8 calculation over the first 4 octets of the ATM cell header. The RXCP-50 verifies the received HCS using the accumulation polynomial, x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the received HCS octet before comparison with the calculated result as required by the ATM Forum UNI specification, and ITU-T Recommendation I.432. The RXCP-50 can be programmed to drop all cells containing an HCS error or to filter cells based on the HCS and the cell header. Filtering according to a particular HCS and the GFC, PTI, and CLP bits of the ATM cell header (the VCI and VPI bits must be all logic 0) is programmable through the RXCP-50 registers.
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More precisely, filtering is performed when filtering is enabled or when HCS errors are found when HCS checking is enabled. Otherwise, all cells are passed on regardless of any error conditions. Cells can be blocked if the HCS pattern is invalid or if the filtering 'Match Pattern' and 'Match Mask' registers are programmed with a certain blocking pattern. ATM Idle cells are filtered by default. For ATM cells, Null cells (Idle cells) are identified by the standardized header pattern of 'H00, 'H00, 'H00 and 'H01 in the first 4 octets followed by the valid HCS octet. While the cell delineation state machine is in the SYNC state, the HCS verification circuit implements the state machine shown in Figure 11. In normal operation, the HCS verification state machine remains in the 'Correction' state. Incoming cells containing no HCS errors are passed to the receive FIFO. Incoming single-bit errors are corrected, and the resulting cell is passed to the FIFO. Upon detection of a single-bit error or a multi-bit error, the state machine transitions to the 'Detection' state. A programmable hysteresis is provided when dropping cells based on HCS errors. When a cell with an HCS error is detected, the RXCP-50 can be programmed to continue to discard cells until m (where m = 1, 2, 4, 8) cells are received with a correct HCS. The mth cell is not discarded (see Figure 11). Note that the dropping of cells due to HCS errors only occurs while the ATMF is in the SYNC state. Cell delineation can optionally be disabled, allowing the RXCP-50 to pass all data bytes it receives.
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Figure 11
- HCS Verification State Diagram
A T M D E L IN E A TIO N S YN C S T A T E
N o E rro rs D ete cte d (P ass C ell)
ALP H A consec utiv e incorrect H CS's (T o HU NT state)
A pp aren t M ulti-B it E rror (D rop C e ll)
C O R R E C TIO N MODE S ingle B it E rro r (C orrect error and pa ss cell)
D rop C e ll D E TE C TIO N MODE
DE LT A consec utiv e correct H CS's (From P RES YNC state)
N o E rro rs D e te cte d in M (M = 1, 2 , 4, or 8) con se cutive ce lls (P ass Last C ell)
9.10 RXFF Receive FIFO The Receive FIFO (RXFF) provides FIFO management and the S/UNI-QJET receive cell interface. The receive FIFO contains four cells. The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. In general, the management functions include filling the receive FIFO, indicating when the receive FIFO contains cells, maintaining the receive FIFO read and write pointers, and detecting FIFO overrun and underrun conditions. The FIFO interface is "UTOPIA Level 2" compliant and accepts a read clock (RFCLK) and read enable signal (RENB). The receive FIFO output bus (RDAT[15:0]) is tri-stated when RENB is logic 1 or if the PHY device address (RADR[4:0]) selected does not match this device's address. The interface indicates the start of a cell (RSOC) and the receive cell available status (RCA and DRCA[4:1]) when data is read from the receive FIFO (using the rising edges
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of RFCLK). The RCA (and DRCA[x]) status changes from available to unavailable when the FIFO is either empty (RCALEVEL0=1) or near empty (RCALEVEL0 is logic 0). This interface also indicates FIFO overruns via a maskable interrupt and register bits. Read accesses while RCA (or DRCA[x]) is a logic 0 will output invalid data. 9.11 CPPM Cell and PLCP Performance Monitor The Cell and PLCP Performance Monitor (CPPM) Block interfaces directly to the SPLR to accumulate bit interleaved parity error events, framing octet error events, and far end block error events in saturating counters. When the PLCP framer (SPLR) declares loss of frame, bit interleaved parity error events, framing octet error events, far end block error events, header check sequence error events are not counted. When an accumulation interval is signaled by a write to the CPPM register address space or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register, the CPPM transfers the current counter values into holding registers and resets the counters to begin accumulating error events for the next interval. The counters are reset in such a manner that error events occurring during the reset period are not missed. 9.12 PRGD Pseudo-Random Sequence Generator/Detector The Pseudo-Random Sequence Generator/Detector (PRGD) block is a software programmable test pattern generator, receiver, and analyzer. Two types of test patterns (pseudo-random and repetitive) conform to ITU-T O.151. The PRGD can be programmed to generate any pseudo-random pattern with length up to 232-1 bits or any user programmable bit pattern from 1 to 32 bits in length. In addition, the PRGD can insert single bit errors or a bit error rate between 10-1 to 10-7. The PRGD can be programmed to check for the presence of the generated pseudo-random pattern. The PRGD can perform an auto-synchronization to the expected pattern, and generate interrupts on detection and loss of the specified pattern. The PRGD can accumulate the total number of bits received and the total number of bit errors in two saturating 32-bit counters. The counters accumulate over an interval defined by writes to the S/UNI-QJET Identification/Master Reset, and Global Monitor Update register (register 006H) or by writes to any PRGD accumulation register. When an accumulation is forced by either method, then the holding registers are updated, and the counters reset to begin accumulating for the next interval. The counters are reset in such a way
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that no events are missed. The data is then available in the holding registers until the next accumulation. In addition to the two counters, a record of the 32 bits received immediately prior to the accumulation is available. The PRGD may also be programmed to check for repetitive sequences. When configured to detect a pattern of length N bits, the PRGD will load N bits from the detected stream, and determine whether the received pattern repeats itself every N subsequent bits. Should it fail to find such a pattern, it will continue loading and checking until it finds a repetitive pattern. All the features (error counting, auto-synchronization, etc.) available for pseudo-random sequences are also available for repetitive sequences. Whenever a PRGD accumulation is forced, the PRGD stores a snapshot of the 32 bits received immediately prior to the accumulation. This snapshot may be examined in order to determine the exact nature of the repetitive pattern received by PRGD. The pseudo-random or repetitive pattern can be inserted/extracted in the PLCP payload (if PLCP framing is enabled) or in the DS3, E3, J2, or Arbitrary framing format payload (if PLCP framing is disabled). It cannot be inserted into the ATM cell payload. 9.13 DS3 Transmitter The DS3 Transmitter (T3-TRAN) Block integrates circuitry required to insert the overhead bits into a DS3 bit stream and produce a B3ZS-encoded signal. The T3-TRAN is directly compatible with the M23 and C-bit parity DS3 formats. Status signals such as far end receive failure (FERF), the alarm indication signal, and the idle signal can be inserted when their transmission is enabled by internal register bits. FERF can also be automatically inserted on detection of any combination of LOS, OOF or RED, or AIS by the T3-FRMR. A valid pair of P-bits is automatically calculated and inserted by the T3-TRAN. When C-bit parity mode is selected, the path parity bits, and far end block error (FEBE) indications are automatically inserted. When enabled for C-bit parity operation, the FEAC channel is sourced by the XBOC bit-oriented code transmitter. The path maintenance data link messages are sourced by the TDPR data link transmitter. These overhead signals can also be overwritten by using the TOH[x] and TOHINS[x] inputs. When enabled for M23 operation, the C-bits are forced to logic 1 with the exception of the C-bit Parity ID bit (first C-bit of the first M-subframe), which is forced to toggle every M-frame.
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The T3-TRAN supports diagnostic modes in which it inserts parity or path parity errors, F-bit framing errors, M-bit framing errors, invalid X or P-bits, line code violations, or all-zeros. User control of each of the overhead bits in the DS3 frame is provided. Overhead bits may be inserted on a bit-by-bit basis from a user supplied data stream. An overhead clock (at 526 kHz) and a DS3 overhead alignment output are provided to allow for control of the user provided stream. 9.14 E3 Transmitter The E3 Transmitter (E3-TRAN) Block integrates circuitry required to insert the overhead bits into an E3 bit stream and produce an HDB3-encoded signal. The E3-TRAN is directly compatible with the G.751 and G.832 framing formats. The E3-TRAN generates the frame alignment signal and inserts it into the incoming serial stream based on either the G.751 or G.832 formats and an alignment pulse applied to it by the SPLT block. All overhead and status bits in each frame format can be individually controlled by register bits or by the transmit overhead stream. While in certain framing format modes, the E3-TRAN generates various overhead bytes according to the following: In G.832 E3 format, the E3-TRAN: * * * * inserts the BIP-8 byte calculated over the preceding frame; inserts the Trail Trace bytes through the Trail Trace Buffer (TTB) block; inserts the FERF bit via a register bit or, optionally, when the E3-FRMR declares OOF, or when the loss of cell delineation (LCD) defect is declared; inserts the FEBE bit, which is set to logic 1 when one or more BIP-8 errors are detected by the receive framer. If there are no BIP-8 errors indicated by the E3-FRMR, the E3-TRAN sets the FEBE bit to logic 0; inserts the Payload Type bits based on the register value set by the microprocessor; inserts the Tributary Unit multiframe indicator bits either via the TOH overhead stream or by register bit values set by the microprocessor; inserts the Timing Marker bit via a register bit;
* * *
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*
inserts the Network Operator (NR) byte from the TDPR block when the TNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 1; otherwise, the NR byte is set to all ones. The NR byte can be overwritten by using the TOH[x] and TOHINS[x] input pins. All 8 bits of the Network Operator byte are available for use as a datalink; inserts the General Purpose Communication Channel (GC) byte from the TDPR block when the TNETOP bit in the S/UNI-QJET Data Link and FERF Control register is logic 0; otherwise, the byte is set to all ones. The GC byte can be overwritten by using the TOH[x] and TOHINS[x] input pins.
*
In G.751 E3 mode, the E3-TRAN : * * inserts the Remote Alarm Indication bit (bit 11 of the frame) either via a register bit or, optionally, when the E3-FRMR declares OOF; inserts the National Use reserved bit (bit 12 of the frame) either as a fixed value through a register bit or from the TDPR block as configured by the TNETOP bit in the S/UNI-QJET Data Link and FERF Control register and the NATUSE bit in the E3 TRAN Configuration register; optionally identifies the tributary justification bits and stuff opportunity bits as either overhead or payload to SPLT for payload mappings that take advantage of the full bandwidth.
*
Further, the E3-TRAN can provide insertion of bit errors in the framing pattern or in the parity bits, and insertion of single line code violations for diagnostic purposes. Most of the overhead bits can be overwritten by using the TOH[x] and TOHINS[x] input pins. 9.15 J2 Transmitter The J2 Transmitter (J2-TRAN) Block integrates circuitry required to insert the overhead bits into an J2 bit stream and produce a B8ZS-encoded signal. The J2-TRAN is directly compatible with the framing format specified in G.704 and NTT Technical Reference for High-Speed Digital Leased Circuit Services. The J2-TRAN generates the frame alignment signal and inserts it into the incoming serial stream. All overhead and status bits in each frame format can be individually controlled by either register bits or by the transmit overhead stream.
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The J2-TRAN: * * * * * * inserts the CRC-5 bits calculated over the preceding multiframe; inserts the x-bits through microprocessor programmable register bits; inserts the a-bit through a microprocessor programmable register bit; inserts the m-bit data link through the TDPR block; inserts payload AIS or physical layer AIS through microprocessor programmable register bits; inserts RAI over the m-bits, overwriting HDLC frames, by using the XBOC block or through automatic activation upon detection of certain remote alarm conditions.
The J2-TRAN allows overwriting of any of the overhead bits by using the TOH[x], TOHINS[x], TOHFP[x], and TOHCLK[x] overhead signals. Further, the J2-TRAN can provide insertion of single bit errors in the framing pattern or in the CRC-5 bits, and insertion of single line code violations for diagnostic purposes. 9.16 XBOC Bit Oriented Code Generator The Bit Oriented Code Generator (XBOC) Block transmits 63 of the possible 64 bit oriented codes (BOC) in the C-bit parity Far End Alarm and Control (FEAC) channel. A BOC is a 16-bit sequence consisting of 8 ones, a zero, 6 code bits, and a trailing zero (111111110xxxxxx0) which is repeated as long as the code is not 111111. The code to be transmitted is programmed by writing the XBOC Code Register. The 64th code (111111) is similar to the HDLC idle sequence and is used to disable the transmission of any bit oriented codes. When transmission is disabled, the FEAC channel is set to all ones. 9.17 TDPR Facility Data Link Transmitter The Facility Data Link Transmitter (TDPR) provides a serial data link for the C-bit parity path maintenance data link in DS3, the serial Network Operator byte or the General Purpose datalink in G.832 E3, the National Use bit datalink in G.751 E3, or the m-bit datalink in J2. The TDPR is used under microprocessor control to transmit HDLC data frames. It performs all of the data serialization, CRC generation, zero-bit stuffing, as well as flag, and abort sequence insertion. Upon completion of the message, a CRC-CCITT frame check sequence (FCS) can be
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appended, followed by flags. If the TDPR transmit data FIFO underflows, an abort sequence is automatically transmitted. When enabled, the TDPR continuously transmits flags (01111110) until data is ready to be transmitted. Data bytes to be transmitted are written into the TDPR Transmit Data Register. The TDPR automatically begins transmission of data once at least one complete packet is written into its FIFO. All complete packets of data will be transmitted if no error condition occurs. After the last data byte of a packet, the CRC FCS (if CRC insertion has been enabled) and a flag, or just a flag (if CRC insertion has not been enabled) is transmitted. The TDPR then returns to the transmission of flag characters until the next packet is available for transmission. The TDPR will also force transmission of the FIFO data once the FIFO depth has surpassed the programmable upper limit threshold. Transmission commences regardless of whether or not a packet has been completely written into the FIFO. The user must be careful to avoid overfilling the FIFO. Underruns can only occur if the packet length is greater than the programmed upper limit threshold because, in such a case, transmission will begin before a complete packet is stored in the FIFO. An interrupt can be generated once the FIFO depth has fallen below a user configured lower threshold as an indicator for the user to write more data. Interrupts can also be generated if the FIFO underflows while transmitting a packet, when the FIFO is full, or if the FIFO is overrun. If there are more than five consecutive ones in the raw transmit data or in the CRC data, a zero is stuffed into the serial data output. This prevents the unintentional transmission of flag or abort sequences. Abort sequences (01111111 sequence where the 0 is transmitted first) can be continuously transmitted at any time by setting a control bit. During packet transmission, an underrun situation can occur if data is not written to the TDPR Transmit Data register before the previous byte has been depleted. In this case, an abort sequence is transmitted, and the controlling processor is notified via the UDR register bit. An abort sequence will also be transmitted if the user overflows the FIFO with a packet of length greater than 128 bytes. Overflows where other complete packets are still stored in the FIFO will not generate an abort. Only the packet which caused the overflow is corrupted and an interrupt is generated to the user via the OVR register bit. The other packets remain unaffected. When the TDPR is disabled, a logical 1 (Idle) is inserted in the path maintenance data link.
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9.18 SPLT SMDS PLCP Layer Transmitter The SMDS PLCP Layer Transmitter (SPLT ) Block integrates circuitry to support DS1, DS3, E1, and G.751 E3 based PLCP frame insertion. The SPLT automatically inserts the framing (A1, A2) and path overhead identification (POHID) octets and provides registers or automatic generation of the F1, B1, G1, M2, M1 and C1 octets. Registers are provided for the path user channel octet (F1) and the path status octet (G1). The bit interleaved parity octet (B1) and the FEBE subfield are automatically inserted. The DQDB management information octets, M1 and M2 are generated. The type 0 and type 1 patterns described in TA-TSY-000772 are automatically inserted. The type 1 page counter may be reset using a register bit in the SPLT Configuration register. Note that this feature is not required for the ATM Forum compliant DS3 UNI. For this application, the M1 and M2 octets must be set to all zeros. The PLCP transmit frame C1 cycle/stuff counter octet and the transmit stuffing pattern can be referenced to the REF8KI input pin. Alternately, a fixed stuffing pattern may be inserted into the C1 cycle/stuff counter octet. A looped timing operating mode is provided where the transmit PLCP timing is derived from the received timing. In this mode, the C1 stuffing is generated based on the received stuffing pattern as determined by the SPLR block. When DS1 or E1 PLCP format is enabled, the pattern 00H is inserted. When DS3 PLCP format is enabled, the C1 octet indicates the phase of the 375 s nibble stuffing opportunity cycle. During frame one of the three frame cycle, the pattern FFH is inserted in the C1 octet, indicating a 13 nibble trailer length. During frame two, the pattern 00H is inserted, indicating a 14 nibble trailer length. During frame three, the pattern 66H or 99H is inserted, indicating a 13 or 14 nibble trailer length respectively. When configured for G.751 E3 PLCP frame format, the C1 octet is used to indicate the number of octets stuffed in the trailer. The following table shows the C1 octet pattern for each of the possible octet stuff lengths:
Stuff Length 17
C1(Hex) 3B
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Stuff Length 18 19 20 21
C1(Hex) 4F 75 9D A7
The SPLT block generates a stuff length pattern of 18, 19 or 20 octets determined by the phase alignment of the start of the G.751 E3 frame and the start of the E3 PLCP frame. The REF8KI input is provisioned to loop time the PLCP transmit frame to an externally applied 8 kHz reference. The Zn, growth octets are set to 00H. The Zn octets may be inserted from an external device via the path overhead stream input, TPOH. 9.19 TXCP-50 Transmit Cell Processor The Transmit Cell Processor (TXCP-50) Block integrates circuitry to support ATM cell payload scrambling, header check sequence (HCS) generation, and idle/unassigned cell generation. The TXCP-50 scrambles the cell payload field using the self synchronizing scrambler with polynomial x43 + 1. The header portion of the cells may optionally also be scrambled. Note that cell payload scrambling may be disabled in the S/UNI-QJET, though it is required by ITU-T Recommendation I.432. The ATM Forum DS3 UNI specification requires that cell payloads are scrambled for the DS3 physical layer interface. However, to ensure backwards compatibility with older equipment, the payload scrambling may be disabled. The HCS is generated using the polynomial, x8 + x2 + x + 1. The coset polynomial x6 + x4 + x2 + 1 is added (modulo 2) to the calculated HCS octet as required by the ATM Forum UNI specification, and ITU-T Recommendation I.432. The resultant octet optionally overwrites the HCS octet in the transmit cell. When the transmit FIFO is empty, the TXCP-50 inserts idle/unassigned cells. The idle/unassigned cell header is fully programmable using five internal registers. Similarly, the 48 octet information field is programmed with an 8 bit repeating pattern using an internal register.
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9.20 TXFF Transmit FIFO The Transmit FIFO (TXFF) provides FIFO management and the S/UNI-QJET transmit cell interface. The transmit FIFO contains four cells. The FIFO depth may be programmed to four, three, two, or one cells. The FIFO provides the cell rate decoupling function between the transmission system physical layer and the ATM layer. In general, the management functions include emptying cells from the transmit FIFO, indicating when the transmit FIFO is full, maintaining the transmit FIFO read and write pointers and detecting a FIFO overrun condition. The FIFO interface is "UTOPIA Level 2" compliant and accepts a write clock (TFCLK), a write enable signal (TENB), the start of a cell (TSOC) indication, and the parity bit (TPRTY), and the ATM device address (TADR[4:0]) when data is written to the transmit FIFO (using the rising edges of TFCLK). The interface provides the transmit cell available status (TCA and DTCA[4:1]) which can transition from "available" to "unavailable" when the transmit FIFO is near full (when TCALEVEL0 is logic 0) or when the FIFO is full (when TCALEVEL0 is logic 1) and can accept no more writes. To reduce FIFO latency, the FIFO depth at which TCA and DTCA[x] indicates "full" can be set to one, two, three or four cells by the FIFODP[1:0] bits of TXCP-50 Configuration 2 register. If the programmed depth is less than four, more than one cell may be written after TCA or DTCA[x] is asserted as the TXCP-50 still allows four cells to be stored in its FIFO. This interface also indicates FIFO overruns via a maskable interrupt and register bit, but write accesses while TCA or DTCA[x] is logic 0 are not processed. The TXFF automatically transmits idle cells until a full cell is available to be transmitted. 9.21 TTB Trail Trace Buffer The Trail Trace Buffer (TTB) extracts and sources the trail trace message carried in the TR byte of the G.832 E3 stream. The message is used by the OS to prevent delivery of traffic from the wrong source and is 16 bytes in length. The 16-byte message is framed by the PTI Multiframe Alignment Signal (TMFAS = 'b10000000 00000000). One bit of the TMFAS is placed in the most significant bit of each message byte. In the receive direction, the trail trace message is extracted from the serial overhead stream output by the E3-FRMR. The extracted message is stored in the internal RAM for review by an external microprocessor. By default, the TTB will write the byte of a 16-byte message with its most significant bit set high to the first location in the RAM. The extracted trail trace message is checked for consistency between consecutive multiframes. A message received unchanged three or five times (programmable) is accepted for
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comparison with the copy previously written into the internal RAM by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched messages. In the transmit direction, the TTB sources the trail trace message from the internal RAM for insertion into the TR byte by the E3-TRAN. The TTB also extracts the Payload Type label carried in the MA byte of the G.832 E3 stream. The label is used to ensure that the adaptation function at the trail termination sink is compatible with the adaptation function at the trail termination source. The Payload Type label is check for consistency between consecutive multiframes. A Payload Type label received unchanged for five frames is accepted for comparison with the copy previously written into the TTB by the external microprocessor. Alarms are raised to indicate reception of unstable and mismatched Payload Type label bits. 9.22 JTAG Test Access Port The JTAG Test Access Port block provides JTAG support for boundary scan. The standard JTAG EXTEST, SAMPLE, BYPASS, IDCODE and STCTEST instructions are supported. The S/UNI-QJET identification code is 073460CD hexadecimal. 9.23 Microprocessor Interface The microprocessor interface block provides normal and test mode registers, and the logic required to connect to the microprocessor interface. The normal mode registers are required for normal operation, and test mode registers are used to enhance the testability of the S/UNI-QJET. The register set is accessed as follows: Table 2 - Register Memory Map Address 000H 001H 002H 003H 004H 005H 100H 101H 102H 103H 104H 105H 200H 201H 202H 203H 204H 205H 300H 301H 302H 303H 304H 305H Register S/UNI-QJET Configuration 1 S/UNI-QJET Configuration 2 S/UNI-QJET Transmit Configuration S/UNI-QJET Receive Configuration S/UNI-QJET Data Link and FERF/RAI Control S/UNI-QJET Interrupt Status
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Address 006H 106H 007H 008H 009H 00AH 00BH 00CH 00DH 00EH 00FH 010H 011H 012H013H 014H 015H 016H 017H 018H 019H 01AH 01BH 107H 108H 109H 10AH 10BH 10CH 10DH 10EH 10FH 110H 111H 112H113H 114H 115H 116H 117H 118H 119H 11AH 11BH 206H 207H 208H 209H 20AH 20BH 20CH 20DH 20EH 20FH 210H 211H 212H213H 214H 215H 216H 217H 218H 219H 21AH 21BH 306H 307H 308H 309H 30AH 30BH 30CH 30DH 30EH 30FH 310H 311H 312H313H 314H 315H 316H 317H 318H 319H 31AH 31BH
Register S/UNI-QJET Identification, Master Reset, and Global Monitor Update S/UNI-QJET Reserved S/UNI-QJET Clock Activity Monitor and Interrupt Identification SPLR Configuration SPLR Interrupt Enable SPLR Interrupt Status SPLR Status SPLT Configuration SPLT Control SPLT Diagnostics and G1 Octet SPLT F1 Octet PMON Change of PMON Performance Meters PMON Interrupt Enable/Status PMON Reserved PMON Line Code Violation Event Count LSB PMON Line Code Violation Event Count MSB PMON Framing Bit Error Event Count LSB PMON Framing Bit Error Event Count MSB PMON Excessive Zeros Count LSB PMON Excessive Zeros Count MSB PMON Parity Error Event Count LSB PMON Parity Error Event Count MSB
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Address 01CH 01DH 01EH 01FH 020H 021H 022H 023H 024H 025H 026H 027H 028H02FH 030H 031H 032H 033H 034H 035H 036H037H 038H 039H 11CH 11DH 11EH 11FH 120H 121H 122H 123H 124H 125H 126H 127H 128H12FH 130H 131H 132H 133H 134H 135H 136H137H 138H 139H 21CH 21DH 21EH 21FH 220H 221H 222H 223H 224H 225H 226H 227H 228H22FH 230H 231H 232H 233H 234H 235H 236H237H 238H 239H 31CH 31DH 31EH 31FH 320H 321H 322H 323H 324H 325H 326H 327H 328H32FH 330H 331H 332H 333H 334H 335H 336H337H 338H 339H
Register PMON Path Parity Error Event Count LSB PMON Path Parity Error Event Count MSB PMON FEBE/J2-EXZS Event Count LSB PMON FEBE/J2-EXZS Event Count MSB CPPM Reserved CPPM Change of CPPM Performance Meter CPPM BIP Error Count LSB CPPM BIP Error Count MSB CPPM PLCP Framing Error Event Count LSB CPPM PLCP Framing Error Event Count MSB CPPM PLCP FEBE Count LSB CPPM PLCP FEBE Count MSB CPPM Reserved DS3 FRMR Configuration DS3 FRMR Interrupt Enable DS3 FRMR Interrupt Status DS3 FRMR Status DS3 TRAN Configuration DS3 TRAN Diagnostics DS3 TRAN Reserved E3 FRMR Framing Options E3 FRMR Maintenance Options
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Address 03AH 03BH 03CH 03DH 03EH 03FH 040H 041H 042H 043H 044H 045H 046H 047H 048H 049H 04AH04BH 04CH 04DH 04EH 04FH 050H 051H 052H 13AH 13BH 13CH 13DH 13EH 13FH 140H 141H 142H 143H 144H 145H 146H 147H 148H 149H 14AH14BH 14CH 14DH 14EH 14FH 150H 151H 152H 23AH 23BH 23CH 23DH 23EH 23FH 240H 241H 242H 243H 244H 245H 246H 247H 248H 249H 24AH24BH 24CH 24DH 24EH 24FH 250H 251H 252H 33AH 33BH 33CH 33DH 33EH 33FH 340H 341H 342H 343H 344H 345H 346H 347H 348H 349H 34AH34BH 34CH 34DH 34EH 34FH 350H 351H 352H
Register E3 FRMR Framing Interrupt Enable E3 FRMR Framing Interrupt Indication and Status E3 FRMR Maintenance Event Interrupt Enable E3 FRMR Maintenance Event Interrupt Indication E3 FRMR Maintenance Event Status E3 FRMR Reserved E3 TRAN Framing Options E3 TRAN Status and Diagnostic Options E3 TRAN BIP-8 Error Mask E3 TRAN Maintenance and Adaptation Options J2 FRMR Configuration J2 FRMR Status J2 FRMR Alarm Interrupt Enable J2 FRMR Alarm Interrupt Status J2 FRMR Error/X-bit Interrupt Enable J2 FRMR Error/X-bit Interrupt Status J2 FRMR Reserved J2 TRAN Configuration J2 TRAN Diagnostics J2 TRAN TS97 Signaling J2 TRAN TS98 Signaling RDLC Configuration RDLC Interrupt Control RDLC Status
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Address 053H 054H 055H 056H 057H 058H 059H 05AH 05BH 05CH 05DH 05EH05FH 060H 061H 062H 063H 064H 065H 066H 067H 068H 069H 06AH 06BH 06CH 06DH 153H 154H 155H 156H 157H 158H 159H 15AH 15BH 15CH 15DH 15EH15FH 160H 161H 162H 163H 164H 165H 166H 167H 168H 169H 16AH 16BH 16CH 16DH 253H 254H 255H 256H 257H 258H 259H 25AH 25BH 25CH 25DH 25EH25FH 260H 261H 262H 263H 264H 265H 266H 267H 268H 269H 26AH 26BH 26CH 26DH 353H 354H 355H 356H 357H 358H 359H 35AH 35BH 35CH 35DH 35EH35FH 360H 361H 362H 363H 364H 365H 366H 367H 368H 369H 36AH 36BH 36CH 36DH RDLC Data
Register
RDLC Primary Address Match RDLC Secondary Address Match RDLC Reserved RDLC Reserved TDPR Configuration TDPR Upper Transmit Threshold TDPR Lower Interrupt Threshold TDPR Interrupt Enable TDPR Interrupt Status/UDR Clear TDPR Transmit Data TDPR Reserved RXCP-50 Configuration 1 RXCP-50 Configuration 2 RXCP-50 FIFO/UTOPIA Control & Config RXCP-50 Interrupt Enables and Counter Status RXCP-50 Status/Interrupt Status RXCP-50 LCD Count Threshold (MSB) RXCP-50 LCD Count Threshold (LSB) RXCP-50 Idle Cell Header Pattern RXCP-50 Idle Cell Header Mask RXCP-50 Corrected HCS Error Count RXCP-50 Uncorrected HCS Error Count RXCP-50 Received Cell Count LSB RXCP-50 Received Cell Count RXCP-50 Received Cell Count MSB
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Address 06EH 06FH 070H 071H07FH 080H 081H 082H 083H 084H 085H 086H 087H 088H 089H08FH 090H 091H 092H 093H 094H 095H 096H097H 098H 099H 09AH 09BH 16EH 16FH 170H 171H17FH 180H 181H 182H 183H 184H 185H 186H 187H 188H 189H18FH 180H 181H 182H 183H 184H 195H 196H197H 198H 199H 19AH 19BH 26EH 26FH 270H 271H27FH 280H 281H 282H 283H 284H 285H 286H 287H 288H 289H28FH 290H 291H 292H 293H 294H 295H 296H297H 298H 299H 29AH 29BH 36EH 36FH 370H 371H37FH 380H 381H 382H 383H 384H 385H 386H 387H 388H 389H38FH 390H 391H 392H 393H 394H 395H 396H397H 398H 399H 39AH 39BH
Register RXCP-50 Idle Cell Count LSB RXCP-50 Idle Cell Count RXCP-50 Idle Cell Count MSB RXCP-50 Reserved TXCP-50 Configuration 1 TXCP-50 Configuration 2 TXCP-50 Transmit Cell Status TXCP-50 Interrupt Enable/Status TXCP-50 Idle Cell Header Control TXCP-50 Idle Cell Payload Control TXCP-50 Transmit Cell Counter LSB TXCP-50 Transmit Cell Counter TXCP-50 Transmit Cell Counter MSB TXCP-50 Reserved TTB Control Register TTB Trail Trace Identifier Status TTB Indirect Address Register TTB Indirect Data Register TTB Expected Payload Type Label Register TTB Payload Type Label Control/Status TTB Reserved RBOC Configuration/Interrupt Enable RBOC Status XBOC Code S/UNI-QJET Misc.
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Address 09CH 0A0H 0A1H 0A2H 0A3H 0A4H 0A5H0A7H 0A8H 0A9H 0AAH 0ABH 0ACH 0ADH 0AEH 0AFH 0B0H0FFH 19CH 1A0H 1A1H 1A2H 1A3H 1A4H 1A5H1A7H 1A8H 1A9H 1AAH 1ABH 1ACH 1ADH 1AEH 1AFH 1B0H1FFH 29CH 2A0H 2A1H 2A2H 2A3H 2A4H 2A5H2A7H 2A8H 2A9H 2AAH 2ABH 2ACH 2ADH 2AEH 2AFH 2B0H2FFH 39CH 3A0H 3A1H 3A2H 3A3H 3A4H 3A5H3A7H 3A8H 3A9H 3AAH 3ABH 3ACH 3ADH 3AEH 3AFH 3B0H3FFH
Register S/UNI-QJET FRMR LOF Status. PRGD Control PRGD Interrupt Enable/Status PRGD Length PRGD Tap PRGD Error Insertion PRGD Reserved PRGD Pattern Insertion Register #1 PRGD Pattern Insertion Register #2 PRGD Pattern Insertion Register #3 PRGD Pattern Insertion Register #4 PRGD Pattern Detector Register #1 PRGD Pattern Detector Register #2 PRGD Pattern Detector Register #3 PRGD Pattern Detector Register #4 S/UNI-QJET Reserved S/UNI-QJET Master Test Register Reserved for S/UNI-QJET Test
400H 401H - 7FFH
For all register accesses, CSB must be low.
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10
NORMAL MODE REGISTER DESCRIPTION Normal mode registers are used to configure and monitor the operation of the S/UNI-QJET. Normal mode registers (as opposed to test mode registers) are selected when A[10] is low. Notes on Normal Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. All configuration bits that can be written into can also be read back. This allows the processor controlling the S/UNI-QJET to determine the programming state of the block. 3. Writable normal mode register bits are cleared to logic zero upon reset unless otherwise noted. 4. Writing into read-only normal mode register bit locations does not affect S/UNI-QJET operation unless otherwise noted. 5. Certain register bits are reserved. These bits are associated with megacell functions that are unused in this application. To ensure that the S/UNI-QJET operates as intended, reserved register bits must only be written with the suggested logic levels. Similarly, writing to reserved registers should be avoided. 6. The S/UNI-QJET requires a software initialization sequence in order to guarantee proper device operation and long term reliability. Please refer to Section 12.1 of this document for the details on how to program this sequence.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 000H, 100H, 200H, 300H: S/UNI-QJET Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PLOOP: The PLOOP bit controls the DS3, E3, or J2 payload loopback. When a logic 0 is written to PLOOP DS3, E3, or J2 payload loopback is disabled. When a , logic 1 is written to PLOOP the DS3, E3, or J2 overhead bits are regenerated , and inserted into the received DS3, E3, or J2 stream and the resulting stream is transmitted. Setting the PLOOP bit disables the effect of the TICLK bit in the S/UNI-QJET Transmit Configuration register, thereby forcing flow-through timing. The TFRM[1:0] and RFRM[1:0] bits in the S/UNI-QJET Transmit Configuration and Receive Configuration registers, respectively, must be set to the same value for PLOOP to work properly. DLOOP: The DLOOP bit controls the diagnostic loopback. When a logic 0 is written to DLOOP diagnostic loopback is disabled. When a logic 1 is written to DLOOP , , the transmit data stream is looped in the receive direction. The TFRM[1:0] and RFRM[1:0] bits in the S/UNI-QJET Transmit Configuration and Receive Configuration registers, respectively, must be set to the same value for DLOOP to work properly. The DLOOP should not be set to a logic 1 when either the PLOOP LLOOP or LOOPT bit is a logic 1. When in DS3, E3, or J2 , , modes, the TUNI register bit in the S/UNI-QJET Transmit Configuration register should be set to the same value as the UNI bit in the DS3, E3, or J2 FRMR registers. Type R/W R/W R/W R/W R/W R/W R/W R/W Function 8KREFO DS27_53 TOCTA FRMRONLY LOOPT LLOOP DLOOP PLOOP Default 1 1 0 0 0 0 0 0
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LLOOP: The LLOOP bit controls the line loopback. When a logic 0 is written to LLOOP line loopback is disabled. When a logic 1 is written to LLOOP the , , stream received on RPOS/RDATI and RNEG/RLCV/ROHM is looped to the TPOS/TDATO and TNEG/TOHM outputs. Note that the TPOS, TNEG, and TCLK outputs are referenced to RCLK when LLOOP is logic 1. LOOPT: The LOOPT bit selects the transmit timing source. When a logic 1 is written to LOOPT, the transmitter is loop-timed to the receiver. When loop timing is enabled, the receive clock (RCLK) is used as the transmit timing source. The transmit nibble stuffing is derived from the nibble stuffing in the receive PLCP frame (for DS3 or E3 PLCP frame transmission). The FIXSTUFF bit must be set to logic 0 if the LOOPT bit is set to logic 1. When a logic 0 is written to LOOPT, the transmit clock (TICLK) is used as the transmit timing source. The nibble stuffing is derived from the REF8KI input, or is fixed internally (as determined by the FIXSTUFF bit in the SPLT Configuration Register (for DS3 or E3 PLCP frame transmission only). Setting the LOOPT bit disables the effect of the TICLK and TXREF bits in the S/UNI-QJET Transmit Configuration and S/UNI-QJET Configuration 2 registers respectively, thereby forcing flowthrough timing. FRMRONLY: The FRMRONLY bit controls whether the S/UNI-QJET is operating solely as a DS3, E3, or J2 framer/transmitter. If FRMRONLY is set to logic 1, the PLCP , and ATM blocks are disabled and the RDATO, REF8KO/RFPO/RMFPO, RSCLK, ROVRHD, TFPO/TMFPO, TFPI/TMFPI, and TDATI I/O pins are enabled. The ATM interface inputs are ignored and the outputs are tri-stated. If FRMRONLY is set to logic 0, the PLCP and ATM blocks are enabled and the LCD, RPOH, RPOHCLK, RPOHFP TPOH, TIOHM, and TPOHFP I/O pins , are enabled and the ATM interface inputs and outputs are enabled. TOCTA: The TOCTA bit enables octet-alignment or nibble-alignment of the transmit cell stream to the transmission overhead when the arbitrary transmission format is chosen (TFRM[1:0] = 11 binary and SPLT Configuration register bit EXT = 1). This bit has no effect when DS3, G.751 E3, G.832 E3, J2, T1, or E1 formats are selected since octet or nibble alignment is specified for these formats. When the arbitrary transmission format is chosen and TOCTA is set to logic 1, the ATM cell nibbles or octets are aligned to the arbitrary transmission format overhead boundaries (as set by the TIOHM input). Nibble alignment is chosen if the FORM[1:0] bits in the SPLT Configuration
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are set to 00. Byte alignment is chosen if these FORM[1:0] bits are set to any other value. The number of TICLK periods between transmission format overhead bit positions must be divisible by 4 (for nibble alignment) or 8 (for byte alignment). When TOCTA is set to logic 0, no octet alignment is performed , and there is no restriction on the number of TICLK periods between transmission format overhead bit positions. DS27_53: The DS27_53 bit is used to select between the long data structure (27 words in 16-bit mode and 53 bytes in 8-bit mode) and the short data structure (26 words in 16-bit mode and 52 bytes in 8-bit mode) on the ATM interface. When DS27_53 is set to logic one, the RXCP-50 and TXCP-50 blocks are configured to operate with the long data structure; when DS27_53 is set to logic zero, the RXCP-50 and TXCP-50 are configured to operate with the short data structure. 8KREFO: The 8KREFO bit is used, in conjunction with the PLCPEN bit in the SPLR Configuration Register to select the function of the REF8KO/RPOHFP/RFPO/RMFPO[x] output pin. When PLCPEN is logic 1, the RPOHFP function will be selected and 8KREFO has no effect (note that RPOHFP is inherently an 8kHz reference). If PLCPEN is logic 0, then if 8KREFO is logic 1, then an 8kHz reference will be derived from the RCLK[x] signal and output on REF8KO. If 8KREFO and PLCPEN are both logic 0, then the RXMFPO register bit in the S/UNI-QJET Configuration 2 register will select either the RFPO or RMFPO function.
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Register 001H, 101H, 201H, 301H: S/UNI-QJET Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RXMFPO: The RXMFPO bit controls which of the outputs RMFPO[4:1] or RFPO[4:1] is valid. If RXMFPO is a logic 1, then RMFPO[4:1] will be available. If RXMFPO is a logic 0, then RFPO[4:1] will be available. This bit has effect only if the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is a logic 1. TXMFPO: The TXMFPO bit controls which of the outputs TMFPO[4:1] or TFPO[4:1] is valid. If TXMFPO is a logic 1, then TMFPO[4:1] will be available. If TXMFPO is a logic 0, then TFPO[4:1] will be available. This bit has effect only if the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is a logic 1. The TXGAPEN bit takes precedence over the TXMFPO bit. RXGAPEN: The RXGAPEN bit configures the S/UNI-QJET to enable the RGAPCLK[x] outputs. When RXGAPEN is a logic 1, then the RGAPCLK[x] output is enabled. When RXGAPEN is a logic 0, then the RSCLK[x] output is enabled. The FRMRONLY register bit must be a logic 1 for RXGAPEN to have effect. TXGAPEN: The TXGAPEN bit configures the S/UNI-QJET to enable the TGAPCLK[x] outputs. When TXGAPEN is a logic 1, the TGAPCLK[x] output is enabled. When TXGAPEN is a logic 0, then either the TFPO[x] or TMFPO[x] output is enabled, depending on the setting of the TXMFPO register bit. The FRMRONLY register bit must be a logic 1 for TXGAPEN to have effect.
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function STATSEL[2] STATSEL[1] STATSEL[0] TXMFPI TXGAPEN RXGAPEN TXMFPO RXMFPO
Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
TXMFPI: The TXMFPI bit controls which of the inputs TMFPI[4:1] or TFPI[4:1] is valid. If TXMFPI is a logic 1, then TMFPI[4:1] will be expected. If TXMFPI is a logic 0, then TFPI[4:1] will be expected. This bit has effect only if the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is a logic 1. STATSEL[2:0]: The STATSEL[2:0] bits are used to select the function of the FRMSTAT[4:1] output. The selection is shown in the following table: Table 3 - STATSEL[2:0] Options FRMSTAT output pin indication function E3/DS3 Loss of Frame or J2 extended Loss of Frame (integration periods are selected by the LOFINT[1:0] register bits in the S/UNI-QJET Receive Configuration Register) PLCP Loss of Frame E3/DS3 Out of Frame or J2 Loss of Frame PLCP Out of Frame Alarm Indication Signal (AIS) Loss of Signal DS3 Idle Reserved
STATSEL[2:0] 000
001 010 011 100 101 110 111
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Register 002H, 102H, 202H, 302H: S/UNI-QJET Transmit Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TNEGINV: The TNEGINV bit provides polarity control for outputs TNEG/TOHM. When a logic 0 is written to TNEGINV, the TNEG/TOHM output is not inverted. When a logic 1 is written to TNEGINV, the TNEG/TOHM output is inverted. The TNEGINV bit setting does not affect the loopback data in diagnostic loopback. TPOSINV: The TPOSINV bit provides polarity control for outputs TPOS/TDATO. When a logic 0 is written to TPOSINV , the TPOS/TDATO output is not inverted. When a logic 1 is written to TPOSINV , the TPOS/TDATO output is inverted. The TPOSINV bit setting does not affect the loopback data in diagnostic loopback. TCLKINV: The TCLKINV bit provides polarity control for output TCLK. When a logic 0 is written to TCLKINV, TCLK is not inverted and outputs TPOS/TDATO and TNEG/TOHM are updated on the falling edge of TCLK. When a logic 1 is written to TCLKINV, TCLK is inverted and outputs TPOS/TDATO and TNEG/TOHM are updated on the rising edge of TCLK. TUNI: The TUNI bit enables the S/UNI-QJET to transmit unipolar or bipolar DS3, E3, or J2 data streams. When a logic 1 is written to TUNI, the S/UNI-QJET transmits unipolar DS3, E3, or J2 data on TDATO. When TUNI is logic 1, the TOHM output indicates the start of the DS3 M-Frame (the X1 bit), the start of the E3 frame (bit 1 of the frame), or the first framing bit of the J2 multiframe.
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function TFRM[1] TFRM[0] TXREF TICLK TUNI TCLKINV TPOSINV TNEGINV
Default 0 0 0 0 0 0 0 0
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When a logic 0 is written to TUNI, the S/UNI-QJET transmits B3ZS-encoded DS3 data, HDB3-encoded E3 data, or B8ZS-encoded J2 data on TPOS and TNEG. The TUNI bit has no effect if TFRM[1:0] is set to 11 binary as the output data is automatically configured for unipolar format. TICLK: The TICLK bit selects the transmit clock used to update the TPOS/TDATO and TNEG/TOHM outputs. When a logic 0 is written to TICLK, the buffered version of the input transmit clock, TCLK, is used to update TPOS/TDATO and TNEG/TOHM on the edge selected by the TCLKINV bit. When a logic 1 is written to TICLK, TPOS/TDATO and TNEG/TOHM are updated on the rising edge of TICLK, eliminating the flow-through TCLK signal. The TICLK bit has no effect if the LOOPT, LLOOP or PLOOP bit is a logic 1. , TXREF: The TXREF register bit determines if TICLK[1] and TIOHM/TFPI/TMFPI[1] should be used as the reference transmit clock and overhead/frame pulse, respectively, instead of TICLK[X] and TIOHM/TFPI/TMFPI[X]. If TXREF is set to a logic 1, then TICLK[1] and TIOHM/TFPI/TMFPI[1] will be used as the reference transmit clock and overhead/frame pulse, respectively. If TXREF is set to a logic 0, then TICLK[X] and TIOHM/TFPI/TMFPI[X] will be used as the reference transmit clock and overhead/frame pulse, respectively, for quadrant X. If loop-timing is enabled (LOOPT = 1), the TXREF bit has no effect on the corresponding quadrant. Note that when TXREF is set to logic 1, the unused TICLK[x] and TIOHM/TFPI/TMFPI[x] should be tied to power or ground, not left floating. TFRM[1:0]: The TFRM[1:0] bits determine the frame structure of the transmitted signal according to the following table: Table 4 TFRM[1:0] 00 01 10 - TFRM[1:0] Transmit Frame Structure Configurations Transmit Frame Structure DS3 (C-bit parity or M23 depending on the setting of the CBIT bit in the DS3 TRAN Configuration register) E3 (G.751 or G.832 depending on the setting of the FORMAT[1:0] bits in the E3 TRAN Framing Options register) J2 (G.704 and NTT compliant framing format)
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TFRM[1:0] 11
Transmit Frame Structure DS1/E1/Arbitrary framing format - If the EXT bit in the SPLT Configuration register is a logic 0, then DS1 or E1 direct-mapped or PLCP framing is selected (via the PLCPEN and FORM[1:0] bits in the SPLT Configuration register) and TIOHM[x] should be tied low. If EXT is a logic 1, then the arbitrary framing format is selected and overhead positions are indicated by the TIOHM[x] input pin.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 003H, 103H, 203H, 303H: S/UNI-QJET Receive Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RNEGINV: The RNEGINV bit provides polarity control for input RNEG/RLCV/ROHM. When a logic 0 is written to RNEGINV, the input RNEG/RLCV/ROHM is not inverted. When a logic 1 is written to RNEGINV, the input RNEG/RLCV/ROHM is inverted. The RNEGINV bit setting does not affect the loopback data in diagnostic loopback. RPOSINV: The RPOSINV bit provides polarity control for input RPOS/RDATI. When a logic 0 is written to RPOSINV , the input RPOS/RDATI is not inverted. When a logic 1 is written to RPOSINV , the input RPOS/RDATI is inverted. The RPOSINV bit setting does not affect the loopback data in diagnostic loopback. RCLKINV: The RCLKINV bit provides polarity control for input RCLK. When a logic 0 is written to RCLKINV, RCLK is not inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are sampled on the rising edge of RCLK. When a logic 1 is written to RCLKINV, RCLK is inverted and inputs RPOS/RDATI and RNEG/RLCV/ROHM are sampled on the falling edge of RCLK. RSCLKR: The RSCLKR bit has effect only when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set to logic 1. When RSCLKR is a logic 1, the RDATO, RFPO/RMFPO, and ROVRHD outputs are updated on the rising
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function RFRM[1] RFRM[0] LOFINT[1] LOFINT[0] RSCLKR RCLKINV RPOSINV RNEGINV
Default 0 0 0 0 0 0 0 0
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edge of RSCLK. When RSCLKR is a logic 0, the RDATO, RFPO/RMFPO, and ROVRHD outputs are updated on the falling edge of RSCLK. If the RXGAPEN bit is a logic 1, then RSCLKR affects RGAPCLK in the same manner as it affects RSCLK. LOFINT[1:0] The LOFINT[1:0] bits determine the integration period used for asserting and de-asserting E3 and DS3 Loss of Frame or J2 extended Loss of Frame on the FRMLOF register bit of the S/UNI-QJET FRMR LOF Status register (x9CH) and on the FRMSTAT[4:1] output pins (if this function is enabled by the STATSEL[2:0] register bits of the S/UNI-QJET Configuration 2 Register). The integration times are selected as follows: Table 5 - LOF[1:0] Integration Period Configuration
LOFINT[1:0] Integration Period 00 01 10 11 RFRM[1:0]: The RFRM[1:0] bits determine the expected frame structure of the received signal according to the following table: Table 6 RFRM[1:0] 00 01 10 - RFRM[1:0] Receive Frame Structure Configurations Expected Receive Frame Structure DS3 (C-bit parity or M23 depending on the setting of the CBE bit in the DS3 FRMR Configuration register) E3 (G.751 or G.832 depending on the setting of the FORMAT[1:0] bits in the E3 FRMR Framing Options register) J2 (G.704 and NTT compliant framing format) 3ms 2ms 1ms Reserved
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RFRM[1:0] 11
Expected Receive Frame Structure DS1/E1/Arbitrary framing format - when EXT in the SPLR Configuration register is a logic 0, then DS1 or E1 direct-mapped or PLCP framing is selected (via the PLCPEN and FORM[1:0] bits in the SPLR Configuration register) and the frame alignment is indicated by the ROHM[x] input pin. When EXT is a logic 1, then the arbitrary framing format is selected and overhead bit positions are indicated by the ROHM[x] input pin.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 004H, 104H, 204H, 304H: S/UNI-QJET Data Link and FERF/RAI Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DLINV: The DLINV bit provides polarity control for the DS3 C-bit Parity path maintenance data link which is located in the 3 C-bits of M-subframe 5. When a logic 1 is written to DLINV, the path maintenance data link is inverted before being processed. The rationale behind this bit is as follows: currently ANSI standard T1.107 specifies that the C-bits (which carry the path maintenance data link) be set to all zeros while the AIS maintenance signal is transmitted. The data link is obviously inactive during AIS transmission, and ideally the HDLC idle sequence (all ones) should be transmitted. By inverting the data link, the all zeros C-bit pattern becomes an idle sequence and the data link is terminated gracefully. Although this inversion is currently not specified in ANSI T1.107a, this bit is provided to safe-guard the S/UNI-QJET in case the inversion is required in the future. RNETOP: The RNETOP bit enables the Network Operator Byte (NR) extracted from the G.832 E3 stream to be terminated by the internal HDLC receiver, RDLC. When RNETOP is logic 1, the NR byte is extracted from the G.832 stream and terminated by RDLC. When RNETOP is logic 0, the GC byte is extracted from the G.832 stream and terminated by RDLC. Both the NR byte and the GC byte are extracted and output on the ROH pin for external processing. TNETOP: Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDEN AISEN RBLEN OOFEN LOSEN TNETOP RNETOP DLINV Default 1 1 1 1 1 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
The TNETOP bit enables the Network Operator Byte (NR) inserted in the G.832 E3 stream to be sourced by the internal HDLC transmitter, TDPR. When TNETOP is logic 1, the NR byte is inserted into the G.832 stream through the TDPR block; the GC byte of the G.832 E3 stream is sourced by through the TOH[x] and TOHINS[x] pins. If TOH[x] and TOHINS[x] are not active, then an all ones signal will be inserted into the GC byte. When TNETOP is logic 0, the GC byte is inserted into the G.832 stream through the TDPR block; the NR byte of the G.832 E3 stream is sourced by the TOH[x] and TOHINS[x] pins. If TOH[x] and TOHINS[x] are not active, then an all ones signal will be inserted into the NR byte. For G.751 E3 streams, the National Use bit is sourced by the TDPR block if TNETOP and the NATUSE bit (from the E3 TRAN Configuration Register x41H) are both logic 0. If either TNETOP or NATUSE is logic 1, the National Use bit will be sourced from the NATUSE register bit in register x41H. If the S/UNI-QJET is configured for DS3 or J2 operation, TNETOP has no effect. The DS3 C-bit Parity and J2 datalink is inserted into the DS3 or J2 stream through the internal HDLC transmitter TDPR. The TOH[x] and TOHINS[x] input pins can be used to overwrite the values of these overhead bits in the transmit stream. LOSEN: The LOSEN bit enables the receive loss of signal indication to automatically generate a FERF indication in the transmit stream. This bit operates regardless of framer selected (DS3, E3, or J2). When LOSEN is logic 1, assertion of the LOS indication by the framer causes a FERF (RAI in G.751 or J2 mode) to be transmitted by TRAN for the duration of the LOS assertion. When LOSEN is logic 0, assertion of the LOS indication does not cause transmission of a FERF/RAI. Note that for the RAI to be automatically transmitted when in J2 format, the FEAC[5:0] bits in the XBOC Code register must all be set to logic 1. If the XBOC FEAC code is to be transmitted in J2 mode, LOSEN, OOFEN, AISEN, and LCDEN should all be set to logic 0. OOFEN: The OOFEN bit enables the receive out of frame indication to automatically generate a FERF indication (RAI in G.751 or J2 mode) in the transmit stream. This bit operates when the E3 or J2 framer is selected or when the DS3 framer is selected and the RBLEN bit is logic 0. When OOFEN is logic 1, assertion of the OOF indication by the framer causes a FERF/RAI to be transmitted by TRAN for the duration of the OOF assertion. When OOFEN is
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
logic 0, assertion of the OOF indication does not cause transmission of a FERF/RAI. Note that for the RAI to be automatically transmitted when in J2 format, the FEAC[5:0] bits in the XBOC Code register must all be set to logic 1. If the XBOC FEAC code is to be transmitted in J2 mode, LOSEN, OOFEN, AISEN, and LCDEN should all be set to logic 0. RBLEN: The RBLEN bit enables the receive RED alarm (persistent out of frame) indication to automatically generate a FERF indication in the DS3 transmit stream, or a BIP8 error detection in the E3 G.832 Framer to generate a FEBE indication in the E3 G.832 transmit stream, or an LOF to generate a RLOF indication (A-bit) in the J2 transmit stream. When the E3 G.751 framer is selected, this bit has no effect. When RBLEN is logic 1 and TFRM[1:0] is 00 binary and RFRM[1:0] is 00 binary, assertion of the RED indication by the framer causes a FERF to be transmitted by DS3_TRAN for the duration of the RED assertion. Also, for DS3 frame format, the OOFEN bit is internally forced to logic 0 when RBLEN is logic 1. When RBLEN is logic 0, assertion of the RED indication does not cause transmission of a FERF. When RBLEN is logic 1 and TFRM[1:0] is 01 binary and RFRM[1:0] is 01 binary, any BIP8 error indication by the E3 G.832 framer causes a FEBE to be generated by the E3 G.832 TRAN. When RBLEN is logic 0, BIP8 errors detected by the E3 framer do not cause FEBEs to be generated by the E3_TRAN. When RBLEN is logic 1 and TFRM[1:0] is 10 binary and RFRM[1:0] is 10 binary, any LOF error indication by the J2 framer causes the RLOF bit (also known as the A bit) to be set in the J2 transmit stream. When RBLEN is logic 0, LOF errors detected by the J2 framer do not cause the RLOF bit to be set in the transmit stream. AISEN: The AISEN bit enables the receive alarm indication signal to automatically generate a FERF indication (RAI in G.751 or J2 mode) in the transmit stream. This bit operates regardless of framer selected (DS3, E3, or J2). When AISEN is logic 1, assertion of the AIS indication (physical AIS for J2) by the framer causes a FERF/RAI to be transmitted by TRAN for the duration of the AIS assertion. When AISEN is logic 0, assertion of the AIS indication does not cause transmission of a FERF/RAI. Note that for the RAI to be automatically transmitted when in J2 format, the FEAC[5:0] bits in the XBOC Code register must all be set to logic 1. If the XBOC FEAC code is to be transmitted in J2 mode, LOSEN, OOFEN, AISEN, and LCDEN should all be set to logic 0.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LCDEN: The LCDEN bit enables the receive out of cell delineation indication to automatically generate a FERF indication (RAI in G.751 or J2 mode) in the transmit stream. This bit operates regardless of framer selected (DS3, E3, or J2) but only in ATM mode. When LCDEN is logic 1, assertion of the LCD indication by the receive FIFO causes a FERF/RAI to be transmitted by the transmitter for the duration of the LCD assertion. When LCDEN is logic 0, assertion of the LCD indication does not cause transmission of a FERF/RAI. Note that for the RAI to be automatically transmitted when in J2 format, the FEAC[5:0] bits in the XBOC Code register must all be set to logic 1. If the XBOC FEAC code is to be transmitted in J2 mode, LOSEN, OOFEN, AISEN, and LCDEN should all be set to logic 0.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 005H, 105H, 205H, 305H: S/UNI-QJET Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function SPLRI/TTBI TXCP50I RXCP50I RBOCI/PRGDI FRMRI/LOFI PMONI TDPRI RDLCI Default X X X X X X X X
SPLRI/TTBI, TXCP50I, RXCP50I, RBOCI/PRGDI, FRMRI/LOFI, PMONI, TDPRI, RDLCI: These bits are interrupt status indicators. These bits identify the block that is the source of a pending interrupt. The SPLRI/TTBI bit will be logic 1 if either the SPLR or the TTB block has produced the interrupt. The RBOCI/PRGDI bit will be logic 1 if either the RBOC or PRGD block has produced the interrupt. The FRMRI/LOFI will be logic 1 if either the FRMR (J2, E3, or T3 whichever one is enabled) or the E3, T3, or J2 Extended Loss of Frame signal (FRMLOFI from register x9CH) is the source of the interrupt. This register is typically used by interrupt service routines to determine the source of a S/UNI-QJET interrupt.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 006H: S/UNI-QJET Identification, Master Reset, and Global Monitor Update Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R R R R R R R Function RESET TYPE[3] TYPE[2] TYPE[1] TYPE[0] TIP ID[1] ID[0] Default 0 1 0 0 0 X 1 0
This register is used for global performance monitor updates, global software resets, and for device identification. Writing any value except 80H into this register initiates latching of all performance monitor counts in the PMON, RXCP50, and TXCP-50 blocks in all four quadrants of the S/UNI-QJET. The TIP register bit is used to signal when the latching is complete. The CPPM counter registers are not latched by writing to register 006H. Counters in the CPPM can only be updated by writing to CPPM register addresses (x22H - x2FH). RESET: The RESET bit allows software to asynchronously reset the S/UNI-QJET. The software reset is equivalent to setting the RSTB input pin low, except that the S/UNI-QJET Master Test Register is not affected. When a logic 1 is written to RESET, the S/UNI-QJET is reset. When a logic 0 is written to RESET, the reset is removed. The RESET bit must be explicitly set and cleared by writing the corresponding logic value to this register. TYPE[3:0]: The TYPE[3:0] bits allow software to identify this device as the S/UNI-QJET member of the S/UNI family of products. TIP: The TIP bit is set to a logic one when any value is written to this register. Such a write initiates an accumulation interval transfer and loads all the
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
performance meter registers in the PMON, RXCP-50, and TXCP-50 blocks in all four quadrants of the S/UNI-QJET. TIP remains high while the transfer is in progress, and is set to a logic zero when the transfer is complete. TIP can be polled by a microprocessor to determine when the accumulation interval transfer is complete. Note that all the transmit and receive line side clocks must be toggling for TIP to be cleared. ID[1:0]: The ID[1:0] bits allows software to identify the version level of the S/UNI-QJET.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 007H, 107H, 207H, 307H: S/UNI-QJET Clock Activity Monitor and Interrupt Identification Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RFCLKA: The RFCLKA bit monitors for low to high transitions on the RFCLK input. RFCLKA is set high on a rising edge of RFCLK, and is set low when this register is read. TFCLKA: The TFCLKA bit monitors for low to high transitions on the TFCLK input. TFCLKA is set high on a rising edge of TFCLK, and is set low when this register is read. TICLKA: The TICLKA bit monitors for low to high transitions on the TICLK[x] input. TICLKA is set high on a rising edge of TICLK[x], and is set low when this register is read. RCLKA: The RCLKA bit monitors for low to high transitions on the RCLK[x] input. RCLKA is set high on a rising edge of RCLK[x], and is set low when this register is read. INT[4:1]: The INT[4:1] bits identify which of the four quadrants of the S/UNI-QJET have generated the current interrupt. When the INT[x] bit is set to logic 1, then the Xth quadrant has generated the interrupt. The particular block(s) within that
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Type R R R R R R R R
Function INT[4] INT[3] INT[2] INT[1] RCLKA TICLKA TFCLKA RFCLKA
Default X X X X X X X X
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
quadrant which generated the interrupt can be identified by reading the corresponding quadrant's S/UNI-QJET Interrupt Status Register. When the INT[x] bit is set to logic 0, then the Xth quadrant has not generated an interrupt. Note that the INT[4:1] bits are valid only in register address 007H.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 008H, 108H, 208H, 308H: SPLR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT: The EXT bit disables the internal transmission system sublayer timeslot counter from identifying DS1, DS3, E1, J2, E3 G.751, or E3 G.832 overhead bits. The EXT bit allows transmission formats that are unsupported by the internal timeslot counter to be supported using the ROHM[x] input. When a logic 0 is written to EXT, input transmission system overhead (for DS1, DS3, E1, J2, E3 G.751, and E3 G.832 formats) is indicated using the internal timeslot counter. This counter is synchronized to the transmission system frame alignment using the ROHM[x] (for DS1 or E1 ATM direct-mapped formats), or by the integral framer block (for the DS3, J2, E3 G.751, or E3 G.832 formats). When a logic 1 is written to EXT, indications on ROHM[x] identify each transmission system overhead bit. PLCPEN: The PLCPEN bit enables PLCP framing. When a logic 1 is written to PLCPEN, PLCP framing is enabled. The PLCP format is specified by the FORM[1:0] bits in this register. When a logic 0 is written to PLCPEN, PLCP related functions in the SPLR block are disabled. PLCPEN must be programmed to logic 0 for E3 G.832, J2, and arbitrary framing formats. REFRAME: The REFRAME bit is used to trigger reframing. When a logic 1 is written to REFRAME, the S/UNI-QJET is forced out of PLCP frame and a new search R/W Type R/W R/W R/W R/W R/W R/W Function FORM[1] FORM[0] Reserved Reserved REFRAME PLCPEN Unused EXT Default 0 0 0 0 0 0 X 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
for frame alignment is initiated. Note that only a logic 0 to logic 1 transition of the REFRAME bit triggers reframing; multiple write operations are required to ensure such a transition. FORM[1:0]: The FORM[1:0] bits select the PLCP frame format as shown below. These bits must be set to "11" if E1 direct mapped mode is being used (PLCPEN=0 and EXT=1). Table 7 FORM[1] 0 0 1 1 - SPLR FORM[1:0] Configurations FORM[0] 0 1 0 1 PLCP Framing Format DS3 E3 G.751 DS1 E1
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 009H, 109H, 209H, 309H: SPLR Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFE: The OOFE bit enables interrupt generation when a PLCP out of frame defect is declared or removed. The interrupt is enabled when a logic 1 is written. LOFE: The LOFE bit enables interrupt generation when a PLCP loss of frame defect is declared or removed. The interrupt is enabled when a logic 1 is written. YELE: The YELE bit enables interrupt generation when a PLCP yellow alarm defect is declared or removed. The interrupt is enabled when a logic 1 is written. FEE: The FEE bit enables interrupt generation when the S/UNI-QJET detects a PLCP framing octet error. The interrupt is enabled when a logic 1 is written. BIPEE: The BIPEE bit enables interrupt generation when the S/UNI-QJET detects a PLCP bit interleaved parity error. The interrupt is enabled when a logic 1 is written. R/W R/W R/W R/W R/W R/W R/W Type Function Unused FEBEE COLSSE BIPEE FEE YELE LOFE OOFE Default X 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
COLSSE: The COLSSE bit enables interrupt generation when the S/UNI-QJET detects a change of PLCP link status. The interrupt is enabled when a logic 1 is written. FEBEE: The FEBEE bit enables interrupt generation when the S/UNI-QJET detects a PLCP far end block error. The interrupt is enabled when a logic 1 is written.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00AH, 10AH, 20AH, 30AH: SPLR Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFI: The OOFI bit is set to logic 1 when a PLCP out of frame defect is detected or removed. The OOF defect state is contained in the SPLR Status Register. The OOFI bit position is set to logic 0 when this register is read. LOFI: The LOFI bit is set to logic 1 when a PLCP loss of frame defect is detected or removed. The LOF defect state is contained in the SPLR Status Register. The LOFI bit position is set to logic 0 when this register is read. YELI: The YELI bit is set to logic 1 when a PLCP yellow alarm defect is detected or removed. The yellow alarm defect state is contained in the SPLR Status Register. The YELI bit position is set to logic 0 when this register is read. FEI: The FEI bit is set to logic 1 when a PLCP framing octet error is detected. A framing octet error is generated when one or more errors are detected in the framing alignment octets (A1, and A2), or the path overhead identification octets. The FEI bit position is set to logic 0 when this register is read. BIPEI: The BIPEI bit is set to logic 1 when a PLCP bit interleaved parity (BIP) error is detected. BIP errors are detected using the B1 byte in the PLCP path overhead. The BIPEI bit position is set to logic 0 when this register is read.
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Type
Function Unused
Default X X X X X X X X
R R R R R R R
FEBEI COLSSI BIPEI FEI YELI LOFI OOFI
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
COLSSI: The COLSSI bit is set to logic 1 when a PLCP change of link status signal code is detected. The link status signal code is contained in the path status octet (G1). Link status signal codes are required in systems implementing the IEEE-802.6 DQDB protocol. A change of link status event occurs when two consecutive and identical link status codes are received that differ from the current code. The COLSSI bit position is set to logic 0 when this register is read. FEBEI: The FEBEI bit is set to logic 1 when a PLCP far end block error (FEBE) is detected. FEBE errors are indicated in the PLCP path status octet (G1). The FEBEI bit position is set to logic 0 when this register is read.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00BH, 10BH, 20BH, 30BH: SPLR Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFV: The OOFV bit indicates the current PLCP out of frame defect state. When an error is detected in both the A1 and A2 octets or when an error is detected in two consecutive path overhead identifier octets, OOFV is set to logic 1. When the S/UNI-QJET has found two valid, consecutive sets of A1 and A2 octets with two valid and sequential path overhead identifier octets, the OOFV bit is set to logic 0. LOFV: The LOFV bit indicates the current PLCP loss of frame defect state. The loss of frame defect state is an integrated version of the out of frame defect state. The declaration/removal times for the loss of frame defect state depends on the selected PLCP format, and are summarized in the table below: Table 8 - PLCP LOF Declaration/Removal Times Declaration (ms) 1 1.12 25 20 Removal (ms) 12 10 250 200 R R R R R R Type Function Unused LSS[2] LSS[1] LSS[0] Unused YELV LOFV OOFV Default X X X X X X X X
PLCP Format DS3 E3 G.751 DS1 E1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
If the OOF defect state is transient, the LOF counter is decremented at a rate 1/12 (DS3 PLCP) or 1/10 (DS1 or E1 PLCP) or 1/9 (G.751 E3 PLCP) of the incrementing rate. YELV: The YELV bit indicates the current PLCP yellow alarm defect state. YELV is set to a logic 1 when ten or more consecutive frames are received with the yellow bit (contained in the path status octet) set to a logic 1. YELV is set to a logic 0 when ten or more consecutive frames are received with the yellow bit (contained in the path status octet) set to a logic 0. LSS[2:0]: The LSS[2:0] bits contain the current link status signal code. Link status signal codes are required in systems implementing the IEEE-802.6 DQDB protocol. LSS[2:0] is updated when two consecutive and identical link status signal codes are received.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00CH, 10CH, 20CH, 30CH: SPLT Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXT: The EXT bit disables the internal transmission system sublayer timeslot counter from identifying DS1, DS3, E1, J2, E3 G.751, or E3 G.832 overhead bits. The EXT bit allows transmission formats that are unsupported by the internal timeslot counter and must be supported using the TIOHM[x] input. When a logic 0 is written to EXT, input transmission system overhead (for DS1, DS3, E1, J2, E3 G.751, and E3 G.832 formats) is indicated using the internal timeslot counter. This counter flywheels to create the appropriate transmission system alignment. This alignment is indicated on the TOHM[x] output. When a logic 1 is written to EXT, indications on TIOHM[x] identify each transmission system overhead bit. These indications flow through the S/UNI-QJET and appear on the TOHM[x] output where they mark the transmission system overhead placeholder positions in the TDATO[x] stream. EXT should only be set to logic 1 if the TFRM[1:0] bits in the S/UNI-QJET Transmit Configuration register are both set to logic 1 and the arbitrary framing format is desired. PLCPEN: The PLCPEN bit enables PLCP frame insertion. When a logic 1 is written to PLCPEN, DS3, E3 G.751, DS1, or E1 PLCP framing is inserted. The PLCP format is specified by the FORM[1:0] bits in this register. When a logic 0 is written to PLCPEN, PLCP related functions in the SPLT block are disabled. The PLCPEN bit must be set to logic 0 for G.832 E3, J2, and arbitrary framing formats. R/W Type R/W R/W R/W R/W R/W R/W Function FORM[1] FORM[0] M1TYPE M2TYPE FIXSTUFF PLCPEN Unused EXT Default 0 0 0 0 0 0 X 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIXSTUFF: The FIXSTUFF bit controls the transmit PLCP frame octet/nibble stuffing used for DS3 and G.751 E3 PLCP frame formats. When a logic 0 is written to FIXSTUFF, stuffing is determined by the REF8KI input. When a logic 1 is written to FIXSTUFF and the DS3 PLCP frame format is enabled, a nibble is stuffed into the 13 nibble trailer twice every three stuff opportunities (i.e. 13, 14, 14 nibbles). This stuff ratio provides for a nominal PLCP frame rate of 125.0002366 s (an error of 1.9 ppm). When the G.751 E3 PLCP frame format is enabled, 18, 19 or 20 octets are stuffed into the trailer depending on the alignment of the G.751 E3 frame, and the G.751 E3 PLCP frame. This yields a nominal PLCP frame rate of 125 s. M2TYPE: The M2TYPE bit selects the type of code transmitted in the M2 octet. These codes are required in systems implementing the IEEE-802.6 DQDB protocol. When a logic 0 is written to M2TYPE, the fixed pattern type 0 code is transmitted in the M2 octet. When a logic 1 is written to M2TYPE, the 1023 cyclic code pattern (starting with B6 hexadecimal and ending with 8D hexadecimal) is transmitted in the M2 octet. Please refer to TA-TSY-000772, Issue 3 and Supplement 1, for details on the codes. M1TYPE: The M1TYPE bit selects the type of code transmitted in the M1 octet. These codes are required in systems implementing the IEEE-802.6 DQDB protocol. When a logic 0 is written to M1TYPE, the fixed pattern type 0 code is transmitted in the M1 octet. When a logic 1 is written to M1TYPE, the 1023 cyclic code pattern (starting with B6 hexadecimal and ending with 8D hexadecimal) is transmitted in the M1 octet. Please refer to TA-TSY-000772, Issue 3 and Supplement 1, for details on the codes. FORM[1:0]: When EXT = 0 and PLCPEN = 0, the FORM[1:0] bits and the TFRM[1:0] bits in the S/UNI-QJET Transmit Configuration register select the ATM directmapped transmission frame format as shown below. When EXT = 0 and PLCPEN = 1, the FORM[1:0] bits along with the TFRM[1:0] bits select the transmission and PLCP frame format as shown below. When EXT = 1 and TOCTA = 1, then the FORM[1:0] bits control the cell alignment with respect to the transmission overhead given on TIOHM[x] as shown below. The FORM bits have no effect if EXT = 1 and TOCTA = 0.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 9 FORM[1] 0 0 1 1
- SPLT FORM[1:0] Configurations FORM[0] 0 1 0 1 PLCP or ATM direct-mapped Framing Format / Cell alignment DS3 / nibble E3 or J2 / byte DS1 / byte E1 / byte
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00DH, 10DH, 20DH, 30DH: SPLT Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SRCC1: The SRCC1 bit value ORed with input TPOHINS selects the source for the C1 octet on a bit by bit basis. If the OR results in a logic 0, the C1 bit position is derived internally as specified by the FIXSTUFF bit in the SPLT Configuration Register. If the OR results in a logic 1, the C1 bit position is inserted with the value sampled on TPOH. SRCM2: The SRCM2 bit value ORed with input TPOHINS selects the source for the M2 octet on a bit by bit basis. If the OR results in a logic 0, the M2 bit position is derived internally as specified by the M2TYPE bit in the SPLT Configuration Register. If the OR results in a logic 1, the M2 bit position is inserted with the value sampled on TPOH. The M2 octet is set to logic 0 (as required by the ATM Forum User Network Interface specification) by writing this bit position with a logic 1, and connecting the TPOH input to VSS. SRCM1: The SRCM1 bit value ORed with input TPOHINS selects the source for the M1 octet on a bit by bit basis. If the OR results in a logic 0, the M1 bit position is derived internally as specified by the M1TYPE bit in the SPLT Configuration Register. If the OR results in a logic 1, the M1 bit position is inserted with the value sampled on TPOH. The M1 octet is set to logic 0 (as required by the ATM Forum User Network Interface specification) by writing this bit position with a logic 1, and connecting the TPOH input to VSS. R/W R/W R/W R/W R/W R/W R/W Type Function Unused SRCZN SRCF1 SRCB1 SRCG1 SRCM1 SRCM2 SRCC1 Default X 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
SRCG1: The SRCG1 bit value ORed with input TPOHINS selects the source for the G1 octet on a bit by bit basis. If the OR results in a logic 0, the G1 bit position is derived internally as required. If the OR results in a logic 1, the G1 bit position is inserted with the value sampled on TPOH. SRCB1: The SRCB1 bit value ORed with input TPOHINS selects the source for the B1 octet on a bit by bit basis. If the OR results in a logic 0, the internally calculated bit interleaved parity value is inserted in the B1 bit position. If the OR results in a logic 1, the B1 bit position is inserted with the value sampled on TPOH. SRCF1: The SRCF1 bit value ORed with input TPOHINS selects the source for the F1 octet on a bit by bit basis. If the OR results in a logic 0, the F1 bit position is determined by the SPLT F1 Octet Register. If the OR results in a logic 1, the F1 bit position is inserted with the value sampled on TPOH. SRCZN: The SRCZN bit value ORed with input TPOHINS selects the source for the Zn octets (where n=1 to 4 for the DS1 or E1 PLCP frame formats, n=1 to 6 for the DS3 PLCP frame format, and n=1 to 3 for the G.751 E3 PLCP frame format) on a bit by bit basis. If the OR results in a logic 0, the Zn bit position is forced to a logic 0. If the OR results in a logic 1, the Zn bit position is inserted with the value sampled on TPOH.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00EH, 10EH, 20EH, 30EH: SPLT Diagnostics and G1 Octet Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSS[2:0]: The LSS[2:0] bits control the value inserted in the link status signal code bit positions of the path status octet (G1). These bits should be written with logic 0 when implementing an ATM Forum UNI-compliant DS3 interface. YEL: The YEL bit controls the yellow signal bit position in the path status octet (G1). When a logic 1 is written to YEL, the PLCP yellow alarm signal is transmitted. DFEBE: The DFEBE bit controls the insertion of far end block errors in the PLCP frame. When DFEBE is written with a logic 1, a single FEBE is inserted each PLCP frame. When DFEBE is written with a logic 0, FEBEs are indicated based on receive PLCP bit interleaved parity errors. DB1: The DB1 bit controls the insertion of bit interleaved parity (BIP) errors in the PLCP frame. When DB1 is written with a logic 1, a single BIP error is inserted in each PLCP frame. When DB1 is written with a logic 0, the bit interleaved parity is calculated and inserted normally. DAFRM: The DAFRM bit controls the insertion of frame alignment pattern errors. When DAFRM is written with a logic 1, a single bit error is inserted in each A1
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function DPFRM DAFRM DB1 DFEBE YEL LSS[2] LSS[1] LSS[0]
Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
octet, and in each A2 octet. When DAFRM is written with a logic 0, the frame alignment pattern octets are inserted normally. DPFRM: The DPFRM bit controls the insertion of parity errors in the path overhead identification (POHID) octets. When DPFRM is written with a logic 1, a parity error is inserted in each POHID octet. When DPFRM is written with a logic 0, the POHID octets are inserted normally.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 00FH, 10FH, 20FH, 30FH: SPLT F1 Octet Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 F1[7:0]: The F1[7:0] bits contain the value inserted in the path user channel octet (F1). F1[7] is the most significant bit, and is transmitted first. F1[0] is the least significant bit and is the last bit transmitted in the octet. Type R/W R/W R/W R/W R/W R/W R/W R/W Function F1[7] F1[6] F1[5] F1[4] F1[3] F1[2] F1[1] F1[0] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 010H, 110H, 210H, 310H: Change of PMON Performance Meters Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FEBECH: The FEBECH bit is set to logic 1 if one or more FEBE events (or J2 EXZS events when the J2 framing format is selected) have occurred during the latest PMON accumulation interval. CPERRCH: The CPERRCH bit is set to logic 1 if one or more path parity error events have occurred during the latest PMON accumulation interval. PERRCH: The PERRCH bit is set to logic 1 if one or more parity error events (or J2 CRC-5 errors) have occurred during the latest PMON accumulation interval. EXZS: The EXZS bit is set to logic 1 if one or more summed line code violation events in DS3 mode have occurred during the latest PMON accumulation interval. FERRCH: The FERRCH bit is set to logic 1 if one or more F-bit or M-bit error events have occurred during the latest PMON accumulation interval. R R R R R R Type Function Unused Unused LCVCH FERRCH EXZS PERRCH CPERRCH FEBECH Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LCVCH: The LCVCH bit is set to logic 1 if one or more line code violation events have occurred during the latest PMON accumulation interval.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 011H, 111H, 211H, 311H: PMON Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OVR: The OVR bit indicates the overrun status of the PMON holding registers. A logic 1 in this bit position indicates that a previous interrupt has not been cleared before the end of the next accumulation interval, and that the contents of the holding registers have been overwritten. A logic 0 indicates that no overrun has occurred. This bit is reset to logic 0 when this register is read. INTR: The INTR bit indicates the current status of the interrupt signal. A logic 1 in this bit position indicates that a transfer of counter values to the holding registers has occurred; a logic 0 indicates that no transfer has occurred. The INTR bit is set to logic 0 when this register is read. INTE: The INTE bit enables the generation of an interrupt when the PMON counter values are transferred to the holding registers. When a logic 1 is written to INTE, the interrupt generation is enabled. R/W R R Type Function Unused Unused Unused Unused Unused INTE INTR OVR Default X X X X X 0 X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 014H, 114H, 214H, 314H: PMON Line Code Violation Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function LCV[7] LCV[6] LCV[5] LCV[4] LCV[3] LCV[2] LCV[1] LCV[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 015H, 115H, 215H, 315H: PMON Line Code Violation Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCV[15:0]: LCV[15:0] represents the number of DS3, E3, or J2 line code violation errors that have been detected since the last time the LCV counter was polled. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the LCV Error Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 3 RCLK[x] cycles to complete. Type R R R R R R R R Function LCV[15] LCV[14] LCV[13] LCV[12] LCV[11] LCV[10] LCV[9] LCV[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 016H, 116H, 216H, 316H: PMON Framing Bit Error Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FERR[7] FERR[6] FERR[5] FERR[4] FERR[3] FERR[2] FERR[1] FERR[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 017H, 117H, 217H, 317H: PMON Framing Bit Error Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FERR[9:0]: FERR[9:0] represents the number of DS3 F-bit and M-bit errors, or E3 or J2 framing pattern errors, that have been detected since the last time the framing error counter was polled. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the FERR Error Event Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK[x] cycles to complete in DS3 mode and 3 RCLK[x] cycles to complete in E3 and J2 mode. This counter is paused when the corresponding framer has lost frame alignment. R R Type Function Unused Unused Unused Unused Unused Unused FERR[9] FERR[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 018H, 118H, 218H, 318H: PMON Excessive Zero Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function EXZS[7] EXZS[6] EXZS[5] EXZS[4] EXZS[3] EXZS[2] EXZS[1] EXZS[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 019H, 119H, 219H, 319H: PMON Excessive Zero Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXZS[15:0]: In DS3 mode, EXZS[15:0] represents the number of summed Excessive Zeros (EXZS) that occurred during the previous accumulation interval. One or more excessive zeros occurrences within an 85 bit DS3 information block is counted as one summed excessive zero. Excessive zeros are accumulated by this register only when the EXZSO and EXZDET are logic 1 in the DS3 FRMR Additional Configuration Register. This register accumulates summed line code violations when the EXZSO is logic 0. The count of summed line code violations is defined as the number of DS3 information blocks (85 bits) that contain one or more line code violations since the last time the summed LCV counter was polled. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the EXZS Event Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK[x] cycles to complete in DS3 mode and a maximum of 500 RCLK[x] cycles to complete in G.832 E3 mode. Type R R R R R R R R Function EXZS[15] EXZS[14] EXZS[13] EXZS[12] EXZS[11] EXZS[10] EXZS[9] EXZS[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01AH, 11AH, 21AH, 31AH: PMON Parity Error Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PERR[7] PERR[6] PERR[5] PERR[4] PERR[3] PERR[2] PERR[1] PERR[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01BH, 11BH, 21BH, 31BH: PMON Parity Error Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PERR[15:0]: PERR[15:0] represents the number of DS3 P-bit errors, the number of E3 G.832 BIP-8 errors or the number of J2 CRC-5 errors that have been detected since the last time the parity error counter was polled. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the PERR Error Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK[x] cycles to complete in DS3 mode and 3 RCLK[x] cycles to complete in E3 and J2 mode. This counter is paused when the corresponding framer has lost frame alignment. Type R R R R R R R R Function PERR[15] PERR[14] PERR[13] PERR[12] PERR[11] PERR[10] PERR[9] PERR[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01CH, 11CH, 21CH, 31CH: PMON Path Parity Error Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function CPERR[7] CPERR[6] CPERR[5] CPERR[4] CPERR[3] CPERR[2] CPERR[1] CPERR[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01DH, 11DH, 21DH, 31DH: PMON Path Parity Error Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CPERR[13:0]: When configured for DS3 applications, CPERR[13:0] represents the number of DS3 path parity errors that have been detected since the last time the DS3 path parity error counter was polled. This counter is forced to zero when the S/UNI-QJET is configured for either J2 and E3 applications. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the CPERR Error Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK[x] cycles to complete. This counter is paused when the corresponding framer has lost frame alignment. R R R R R R Type Function Unused Unused CPERR[13] CPERR[12] CPERR[11] CPERR[10] CPERR[9] CPERR[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01EH, 11EH, 21EH, 31EH: PMON FEBE/J2-EXZS Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FEBE/J2-EXZS[7] FEBE/J2-EXZS[6] FEBE/J2-EXZS[5] FEBE/J2-EXZS[4] FEBE/J2-EXZS[3] FEBE/J2-EXZS[2] FEBE/J2-EXZS[1] FEBE/J2-EXZS[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 01FH, 11FH, 21FH, 31FH: PMON FEBE/J2-EXZS Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R Type Function Unused Unused FEBE/J2-EXZS[13] FEBE/J2-EXZS[12] FEBE/J2-EXZS[11] FEBE/J2-EXZS[10] FEBE/J2-EXZS[9] FEBE/J2-EXZS[8] Default X X X X X X X X
FEBE/J2-EXZS[13:0]: FEBE/J2-EXZS[13:0] represents the number of DS3 or E3 G.832 far end block errors that have been detected since the last time the FEBE error counter was polled. In J2 mode, FEBE/J2-EXZS[13:0] represents the number of Excessive Zeros (EXZS is a string of 8 or more consecutive zeros) that have occurred during the previous accumulation interval. The counter (and all other counters in the PMON) is polled by writing to any of the PMON register addresses (x14H to x1FH) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Such a write transfers the internally accumulated count to the FEBE Event Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer and reset is carried out in a manner that coincident events are not lost. The transfer takes 255 RCLK[x] cycles to complete in DS3 mode and 3 RCLK[x] cycles to complete in E3 and J2 mode.
This counter is paused when the corresponding framer has lost frame alignment.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 021H, 121H, 221H, 321H: CPPM Change of CPPM Performance Meters Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 BIPECH: The BIPECH bit is set to logic 1 if one or more PLCP bit interleaved parity error events have occurred since the last CPPM accumulation interval. FECH: The FECH bit is set to logic 1 if one or more PLCP frame alignment pattern octet errors, or path overhead identification octet errors have occurred since the last CPPM accumulation interval. FEBECH: The FEBECH bit is set to logic 1 if one or more PLCP far end block error events have occurred since the last CPPM accumulation interval. R R R Type Function Unused Unused Unused Unused Unused FEBECH FECH BIPECH Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 022H, 122H, 222H, 322H: CPPM B1 Error Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function B1E[7] B1E[6] B1E[5] B1E[4] B1E[3] B1E[2] B1E[1] B1E[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 023H, 123H, 223H, 323H: CPPM B1 Error Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 B1E[15:0]: B1E[15:0] represents the number of PLCP bit interleaved parity (BIP) errors that have been detected since the last time the B1 error counter was polled. The counter (and all other counters in the CPPM) is polled by writing to any of the CPPM register addresses (x22H - x2FH). Such a write transfers the internally accumulated count to the B1 Error Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer occurs within 67 RCLK periods (1.5 s for the DS3 bit rate; 1.95s for the E3 bit rate) of the write. The transfer and reset is carried out in a manner that coincident events are not lost. B1 errors are not accumulated when the S/UNI-QJET has declared a PLCP loss of frame defect state. Type R R R R R R R R Function B1E[15] B1E[14] B1E[13] B1E[12] B1E[11] B1E[10] B1E[9] B1E[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 024H, 124H, 224H, 324H: CPPM Framing Error Event Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FE[7] FE[6] FE[5] FE[4] FE[3] FE[2] FE[1] FE[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 025H, 125H, 225H, 325H: CPPM Framing Error Event Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FE[11:0]: FE[11:0] represents the number of PLCP framing pattern octet errors and path overhead identification octet errors that have been detected since the last time the framing error event counter was polled. The counter (and all other counters in the CPPM) is polled by writing to any of the CPPM register addresses (x22H - x2FH). Such a write transfers the internally accumulated count to the Framing Error Event Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer occurs within 67 RCLK periods (1.5 s for the DS3 bit rate; 1.95s for the E3 bit rate) of the write. The transfer and reset is carried out in a manner that coincident events are not lost. Framing error errors are not accumulated when the S/UNI-QJET has declared a PLCP loss of frame defect state. R R R R Type Function Unused Unused Unused Unused FE[11] FE[10] FE[9] FE[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 026H, 126H, 226H, 326H: CPPM FEBE Count LSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FEBE[7] FEBE[6] FEBE[5] FEBE[4] FEBE[3] FEBE[2] FEBE[1] FEBE[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 027H, 127H, 227H, 327H: CPPM FEBE Count MSB Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FEBE[15:0]: FEBE[15:0] represents the number of PLCP far end block errors (FEBE) that have been detected since the last time the FEBE error counter was polled. The counter (and all other counters in the CPPM) is polled by writing to any of the CPPM register addresses (x22H - x2FH). Such a write transfers the internally accumulated count to the FEBE Error Count Registers and simultaneously resets the internal counter to begin a new cycle of error accumulation. This transfer occurs within 67 RCLK periods (1.5 s for the DS3 bit rate; 1.95s for the E3 bit rate) of the write. The transfer and reset is carried out in a manner that coincident events are not lost. FEBE errors are not accumulated when the S/UNI-QJET has declared a PLCP loss of frame defect state. Type R R R R R R R R Function FEBE[15] FEBE[14] FEBE[13] FEBE[12] FEBE[11] FEBE[10] FEBE[9] FEBE[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 030H, 130H, 230H, 330H: DS3 FRMR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CBE: The CBE bit enables the DS3 C-bit parity application. When a logic 1 is written to CBE, C-bit parity mode is enabled. When a logic 0 is written to CBE, the DS3 M23 format is selected. While the C-bit parity application is enabled, C-bit parity error events, far end block errors are accumulated. AISC: The AISC bit controls the algorithm used to detect the alarm indication signal (AIS). When a logic 1 is written to AISC, the algorithm checks that a framed DS3 signal with all C-bits set to logic 0 is observed for a period of time before declaring AIS. The payload contents are checked to the pattern selected by the AISPAT bit. When a logic 0 is written to AISC, the AIS detection algorithm is determined solely by the settings of AISPAT and AISONES register bits (see bit mapping table in the Additional Configuration Register description). REFR: The REFR bit initiates a DS3 reframe. When a logic 1 is written to REFR, the S/UNI-QJET is forced out-of-frame, and a new search for frame alignment is initiated. Note that only a low to high transition of the REFR bit triggers reframing; multiple write operations are required to ensure such a transition. UNI: The UNI bit configures the S/UNI-QJET to accept either dual-rail or single-rail receive DS3 streams. When a logic 1 is written to UNI, the S/UNI-QJET accepts a single-rail DS3 stream on RDATI. The S/UNI-QJET accumulates
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function AISPAT FDET MBDIS M3O8 UNI REFR AISC CBE
Default 1 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
line code violations on the RLCV input. When a logic 0 is written to UNI, the S/UNI-QJET accepts B3ZS-encoded dual-rail data on RPOS and RNEG. M3O8: The M3O8 bit controls the DS3 out of frame decision criteria. When a logic 1 is written to M3O8, DS3 out of frame is declared when 3 of 8 framing bits (F-bits) are in error. When a logic 0 is written to M3O8, the 3 of 16 framing bits in error criteria is used, as recommended in ANSI T1.107 MBDIS: The MBDIS bit disables the use of M-bit errors as a criteria for losing frame alignment. When MBDIS is set to logic 1, M-bit errors are disabled from causing an OOF; the loss of frame criteria is based solely on the number of F-bit errors selected by the M3O8 bit. When MBDIS is set to logic 0, errors in either M-bits or F-bits are enabled to cause an OOF. When MBDIS is logic 0, an OOF can occur when one or more M-bit errors occur in 3 out of 4 consecutive M-frames, or when the F-bit error ratio selected by the M3O8 bit is exceeded. FDET: The FDET bit selects the fast detection timing for AIS, IDLE and RED. When FDET is set to logic 1, the AIS, IDLE, and RED detection time is 2.23 ms; when FDET is set to logic 0, the detection time is 13.5 ms. AISPAT: The AISPAT bit controls the pattern used to detect the alarm indication signal (AIS). When a logic 1 is written to AISPAT, the AIS detection algorithm checks that a framed DS3 signal containing the repeating pattern 1010... is present. The C-bits are checked for the value specified by the AISC bit setting. When a logic 0 is written to AISPAT, the AIS detection algorithm is determined solely by the settings of AISC and AISONES register bits (see bit mapping table in the Additional Configuration Register description).
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 031H, 131H, 231H, 331H: DS3 FRMR Interrupt Enable (ACE=0) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOSE: The LOSE bit enables interrupt generation when a DS3 loss of signal defect is declared or removed. The interrupt is enabled when a logic 1 is written. OOFE: The OOFE bit enables interrupt generation when a DS3 out of frame defect is declared or removed. The interrupt is enabled when a logic 1 is written. AISE: The AISE bit enables interrupt generation when the DS3 AIS maintenance signal is detected or removed. The interrupt is enabled when a logic 1 is written. IDLE: The IDLE bit enables interrupt generation when the DS3 IDLE maintenance signal is detected or removed. The interrupt is enabled when a logic 1 is written. FERFE: The FERFE bit enables interrupt generation when a DS3 far end receive failure defect is declared or removed. The interrupt is enabled when a logic 1 is written. Type R/W R/W R/W R/W R/W R/W R/W R/W Function COFAE REDE CBITE FERFE IDLE AISE OOFE LOSE Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
CBITE: The CBITE bit enables interrupt generation when the S/UNI-QJET detects a change of state in the DS3 application identification channel. The interrupt is enabled when a logic 1 is written. REDE: The REDE bit enables an interrupt to be generated when a change of state of the DS3 RED indication occurs. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status register. When REDE is set to logic 1, the interrupt output, INTB, is set low when the state of the RED indication changes. COFAE: The COFAE bit enables interrupt generation when the S/UNI-QJET detects a DS3 change of frame alignment. The interrupt is enabled when a logic 1 is written.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 031H, 131H, 231H, 331H: DS3 FRMR Additional Configuration Register (ACE=1) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DALGO: The DALGO bit determines the criteria used to decode a valid B3ZS signature. When DALGO is set to logic 1, a valid B3ZS signature is declared and 3 zeros substituted whenever a zero followed by a bipolar violation of the opposite polarity to the last observed BPV is seen. When the DALGO bit is set to logic 0, a valid B3ZS signature is declared and the 3 zeros are substituted whenever a zero followed by a bipolar violation is observed. SALGO: The SALGO bit determines the criteria used to establish a valid B3ZS signature used to map BPVs to line code violation indications. Any BPV that is not part of a valid B3ZS signature is indicated as an LCV. When the SALGO bit is set to logic 1, a valid B3ZS signature is declared whenever a zero followed by a bipolar violation is observed. When SALGO is set to logic 0, a valid B3ZS signature is declared whenever a zero followed by a bipolar violation of the opposite polarity to the last observed BPV is seen. EXZDET: The EXZDET bit determines the type of zero occurrences to be included in the LCV indication. When EXZDET is set to logic 1, the occurrence of an excessive zero generates a single pulse indication that is used to indicate an LCV. When EXZDET is set to logic 0, every occurrence of 3 consecutive zeros generates a pulse indication that is used to indicate an LCV. For example, if a sequence of 15 consecutive zeros were received, with R/W R/W R/W R/W R/W R/W Type Function Unused Unused AISONES BPVO EXZSO EXZDET SALGO DALGO Default X X 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
EXZDET=1 only a single LCV would be indicated for this string of excessive zeros; with EXZDET=0, five LCVs would be indicated for this string (i.e. one LCV for every 3 consecutive zeros). EXZSO: The EXZSO bit enables only summed zero occurrences to be accumulated in the PMON EXZS Count Registers. When EXZSO is set to logic 1, any excessive zeros occurrences over an 85 bit period increments the PMON EXZS counter by one. When EXZSO is set to logic 0, summed LCVs are accumulated in the PMON EXZS Count Registers. A summed LCV is defined as the occurrence of either BPVs not part of a valid B3ZS signature or 3 consecutive zeros (or excessive zeros if EXZDET=1) occurring over an 85 bit period; each summed LCV occurrence increment the PMON EXZS counter by one. BPVO: The BPVO bit enables only bipolar violations to indicate line code violations and be accumulated in the PMON LCV Count Registers. When BPVO is set to logic 1, only BPVs not part of a valid B3ZS signature generate an LCV indication and increment the PMON LCV counter. When BPVO is set to logic 0, both BPVs not part of a valid B3ZS signature, and either 3 consecutive zeros or excessive zeros generate an LCV indication and increment the PMON LCV counter. Table 10 EXZSO 0 0 0 0 1 1 1 1 - DS3 FRMR EXZS/LCV count configurations Register Bit BPVO EXZDET 0 0 0 1 1 0 0 1 1 1 0 1 0 1 0 1 Counter Function PMON EXZ Count PMON LCV Count Summed LCVs BPVs & every 3 consecutive zeros Summed LCVs BPVs & every string of 3+ consecutive zeros Reserved Reserved Reserved Reserved Summed excessive BPVs & every 3 zeros consecutive zeros Summed excessive BPVs & every string of zeros 3+ consecutive zeros Summed excessive Only BPVs zeros Summed excessive Only BPVs zeros
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
AISONES: The AISONES bit controls the pattern used to detect the alarm indication signal (AIS) when both AISPAT and AISC bits in DS3 FRMR Configuration register are logic 0; if either AISPAT or AISC are logic 1, the AISONES bit is ignored. When a logic 0 is written to AISONES, the algorithm checks that a framed all-ones payload pattern (1111...) signal is observed for a period of time before declaring AIS. Only the payload bits are observed to follow an allones pattern, the overhead bits (X, P M, F, C) are ignored. When a logic 1 is , written to AISONES, the algorithm checks that an unframed all-ones pattern (1111...) signal is observed for a period of time before declaring AIS. In this case all the bits, including the overhead, are observed to follow an all-ones pattern. The valid combinations of AISPAT, AISC, and AISONES bits are summarized below: Table 11 AISPAT 1 0 1 - DS3 FRMR AIS Configurations AISC 0 1 1 AISONES X X X AIS Detected Framed DS3 stream containing repeating 1010... pattern; overhead bits ignored. Framed DS3 stream containing C-bits all logic 0; payload bits ignored. Framed DS3 stream containing repeating 1010... pattern in the payload, C-bits all logic 0, and X-bits=1. This can be detected by setting both AISPAT and AISC high, and declaring AIS only when AISV=1 and FERFV=0 (Register x33H). Framed DS3 stream containing all-ones payload pattern; overhead bits ignored. Unframed all-ones DS3 stream.
0 0
0 0
0 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 032H, 132H, 232H, 332H: DS3 FRMR Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOSI: The LOSI bit is set to logic 1 when a loss of signal defect is detected or removed. The LOSI bit position is set to logic 0 when this register is read. OOFI: The OOFI bit is set to logic 1 when an out of frame defect is detected or removed. The OOFI bit position is set to logic 0 when this register is read. AISI: The AISI bit is set to logic 1 when the DS3 AIS maintenance signal is detected or removed. The AISI bit position is set to logic 0 when this register is read. IDLI: The IDLI bit is set to logic 1 when the DS3 IDLE maintenance signal is detected or removed. The IDLI bit position is set to logic 0 when this register is read. FERFI: The FERFI bit is set to logic 1 when a FERF defect is detected or removed. The FERFI bit position is set to logic 0 when this register is read. Type R R R R R R R R Function COFAI REDI CBITI FERFI IDLI AISI OOFI LOSI Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
CBITI: The CBITI bit is set to logic 1 when a change of state is detected in the DS3 application identification channel. The CBITI bit position is set to logic 0 when this register is read. REDI: The REDI bit indicates that a change of state of the DS3 RED indication has occurred. The DS3 RED indication is visible in the REDV bit location of the DS3 FRMR Status register. When the REDI bit is a logic 1, a change in the RED state has occurred. When the REDI bit is logic 0, no change in the RED state has occurred. COFAI: The COFAI bit is set to logic 1 when a change of frame alignment is detected. A COFA is generated when a new DS3 frame alignment is determined that differs from the last known frame alignment. The COFAI bit position is set to logic 0 when this register is read.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 033H, 133H, 233H, 333H: DS3 FRMR Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOSV: The LOSV bit indicates the current loss of signal defect state. LOSV is a logic 1 when a sequence of 175 zeros is detected on the B3ZS encoded DS3 receive stream. LOSV is a logic 0 when a signal with a ones density greater than 33% for 175 1 bit periods is detected. OOFV: The OOFV bit indicates the current DS3 out of frame defect state. When the S/UNI-QJET has lost frame alignment and is searching for the new alignment, OOFV is set to logic 1. When the S/UNI-QJET has found frame alignment, the OOFV bit is set to logic 0. AISV: The AISV bit indicates the alarm indication signal state. When the S/UNI-QJET detects the AIS maintenance signal, AISV is set to logic 1. IDLV: The IDLV bit indicates the IDLE signal state. When the S/UNI-QJET detects the IDLE maintenance signal, IDLV is set to logic 1. FERFV: The FERFV bit indicates the current far end receive failure defect state. When the S/UNI-QJET detects an M-frame with the X1 and X2 bits both set to zero, FERFV is set to logic 1. When the S/UNI-QJET detects an M-frame with the X1 and X2 bits both set to one, FERFV is set to logic 0.
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Type R/W R R R R R R R
Function ACE REDV CBITV FERFV IDLV AISV OOFV LOSV
Default 0 X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
CBITV: The CBITV bit indicates the application identification channel (AIC) state. CBITV is set to logic 1 (indicating the presence of the C-bit parity application) when the AIC bit is set high for 63 consecutive M-frames. CBITV is set to logic 0 (indicating the presence of the M23 or SYNTRAN applications) when AIC is set low for 2 or more M-frames in the last 15. REDV: The REDV bit indicates the current state of the DS3 RED indication. When the REDV bit is a logic 1, the DS3 FRMR frame alignment acquisition circuitry has been out of frame for 2.23ms (or for 13.5ms when FDET is logic 0). When the REDV bit is logic 0, the frame alignment circuitry has found frame (i.e. OOFV=0) for 2.23ms ( or 13.5ms if FDET=0). ACE: The ACE bit selects the Additional Configuration Register. This register is located at address x31H, and is only accessible when the ACE bit is set to logic 1. When ACE is set to logic 0, the Interrupt Enable register is accessible at address x31H.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 034H, 134H, 234H, 334H: DS3 TRAN Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CBIT: The CBIT bit enables the DS3 C-bit parity application. When CBIT is written with a logic 1, C-bit parity is enabled, and the S/UNI-QJET modifies the C-bits as required to include the path maintenance data link, the FEAC channel, the far end block error indication, and the path parity. When CBIT is written with a logic 0, the M23 application is selected, and each C-bit is set to logic 1 by the S/UNI-QJET except for the first C-bit of the frame, which is forced to toggle every frame. Note that the C-bits may be modified as required using the DS3 overhead access port (TOH) regardless of the setting of this bit. FERF: The FERF bit enables insertion of the far end receive failure maintenance signal in the DS3 stream. When FERF is written with a logic 1, the X1 and X2 overhead bit positions are set to logic 0. When FERF is written with a logic 0, the X1 and X2 overhead bit positions in the DS3 stream are set to logic 1. IDL: The IDL bit enables insertion of the idle maintenance signal in the DS3 stream. When IDL is written with a logic 1, the DS3 payload is overwritten with the repeating pattern 1100.... The DS3 overhead bit insertion (X, P M F, , and C) continues normally. When IDL is written with a logic 0, the idle signal is not inserted. R/W Type R/W R/W R/W R/W R/W Function CBTRAN AIS IDL FERF Reserved Unused Unused CBIT Default 0 0 0 0 0 X X 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
AIS: The AIS bit enables insertion of the AIS maintenance signal in the DS3 stream. When AIS is written with a logic 1, the DS3 payload is overwritten with the repeating pattern 1010.... The DS3 overhead bit insertion (X, P M , and F) continues normally. The values inserted in the C-bits during AIS transmission are controlled by the CBTRAN bit in this register. When AIS is written with a logic 0, the AIS signal is not inserted. CBTRAN: The CBTRAN bit controls the C-bit values during AIS transmission. When CBTRAN is written with a logic 0, the C-bits are overwritten with zeros during AIS transmission as specified in ANSI T1.107. When CBTRAN is written with a logic 1, C-bit insertion continues normally (as controlled by the CBIT bit in this register) during AIS transmission. Reserved: The reserved bit must be programmed to logic 0 for proper operation.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 035H, 135H, 235H, 335H: DS3 TRAN Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFEBE: The DFEBE bit controls the insertion of far end block errors in the DS3 stream. When DFEBE is written with a logic 1, and the C-bit parity application is enabled, the three C-bits in M-subframe 4 are set to a logic 0. When DFEBE is written with a logic 0, FEBEs are indicated based on receive framing bit errors and path parity errors. DPERR: The DPERR bit controls the insertion of parity errors (P-bit errors) in the DS3 stream. When DPERR is written with a logic 1, the P-bits are inverted before insertion. When DPERR is written with a logic 0, the parity is calculated and inserted normally. DCPERR: The DCPERR bit controls the insertion of path parity errors in the DS3 stream. When DCPERR is written with a logic 1 and the C-bit parity application is enabled, the three C-bits in M-subframe 3 are inverted before insertion. When DCPERR is written with a logic 0, the path parity is calculated and inserted normally. DMERR: The DMERR bit controls the insertion of M-bit framing errors in the DS3 stream. When DMERR is written with a logic 1, the M-bits are inverted before insertion. When DMERR is written with a logic 0, the M-bits are inserted normally.
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Type R/W R/W R/W R/W R/W R/W R/W
Function DLOS DLCV Unused DFERR DMERR DCPERR DPERR DFEBE
Default 0 0 X 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
DFERR: The DFERR bit controls the insertion of F-bit framing errors in the DS3 stream. When DFERR is written with a logic 1, the F-bits are inverted before insertion. When DFERR is written with a logic 0, the F-bits are inserted normally. DLCV: The DLCV bit controls the insertion of a single line code violation in the DS3 stream. When DLCV is written with a logic 1, a line code violation is inserted by generating an incorrect polarity of violation in the next B3ZS signature. The data being transmitted must therefore contain periods of three consecutive zeros in order for the line code violation to be inserted. For example, line code violations may not be inserted when transmitting AIS, but may be inserted when transmitting the idle signal. DLCV is automatically cleared upon insertion of the line code violation. DLOS: The DLOS bit controls the insertion of loss of signal in the DS3 stream. When DLOS is written with a logic 1, the data on outputs TPOS/TDATO and TNEG/TOHM is forced to continuous zeros.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 038H, 138H, 238H, 338H: E3 FRMR Framing Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 REFR: A transition from logic 0 to logic 1 in the REFR bit position forces the E3 Framer to initiate a search for frame alignment. The bit must be cleared to logic 0, then set to logic 1 again to initiate subsequent searches for frame alignment. REFRDIS: The REFRDIS bit disables reframing under the consecutive framing bit error condition once frame alignment has been found, leaving reframing to be initiated only by software via the REFR bit. A logic 1 in the REFRDIS bit position causes the FRMR to remain "locked in frame" once initial frame alignment has been found. A logic 0 allows reframing to occur when four consecutive framing patterns are received in error. FORMAT[1:0]: The FORMAT[1:0] bits determine the framing mode used for pattern matching when finding frame alignment and for generating the output status signals. The FORMAT[1:0] bits select one of two framing formats: R/W R/W R/W R/W R/W R/W Type Unused Function X Unused Reserved UNI FORMAT[1] FORMAT[0] REFRDIS REFR X 0 0 0 0 0 0 Default
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 12 FORMAT[1] 0 0 1 1 UNI:
- E3 FRMR FORMAT[1:0] Configurations FORMAT[0] 0 1 0 1 Framing Format Selected G.751 E3 format G.832 E3 format Reserved Reserved
The UNI bit selects the mode of the receive data interface. When UNI is logic 1, the E3-FRMR expects unipolar data on the RDATI input and accepts line code violation indications on the RLCV input. When UNI is logic 0, the E3-FRMR expects bipolar data on the RPOS and RNEG inputs and decodes the pulses according to the HDB3 line code. Reserved: The Reserved bit must be programmed to logic 0 for proper operation.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 039H, 139H, 239H, 339H: E3 FRMR Maintenance Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TMARKDET: The TMARKDET bit determines the persistency check performed on the Timing Marker bit (bit 8 of the G.832 Maintenance and Adaptation byte). When TMARKDET is logic 1, the Timing Marker bit must be in the same state for 5 consecutive frames before the TIMEMK status is changed to that state. When TMARKDET is logic 0, the Timing Marker bit must be in the same state for 3 consecutive frames. When a framing mode other than G.832 is selected, the setting of the TMARKDET bit is ignored. FERFDET: The FERFDET bit determines the persistency check performed on the Far End Receive Failure (FERF) bit (bit 1 of the G.832 Maintenance and Adaptation byte) or on the Remote Alarm indication (RAI) bit (bit 11 of the frame in G.751 mode). When FERFDET is logic 1, the FERF, or RAI, bit must be in the same state for 5 consecutive frames before the FERF/RAI status is changed to that state. When FERFDET is logic 0, the FERF, or RAI, bit must be in the same state for 3 consecutive frames. PYLD&JUST: The PYLD&JUST bit selects whether the justification service bits and the tributary justification bits in framing mode G.751 is indicated as overhead or payload. When PYLD&JUST is logic 1, the justification service bits and the tributary justification bits are indicated as payload to the SPLR. When PYLD&JUST is logic 0, the justification service and tributary justification bits R/W R/W R/W R/W R/W R/W Type Function Unused Unused WORDBIP Reserved WORDERR PYLD&JUST FERFDET TMARKDET Default X X 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
are indicated as overhead to SPLR. For G.751 ATM applications, this bit must be set to logic 1 for correct cell mapping. WORDERR: The WORDERR bit selects whether the framing bit error indication pulses accumulated in PMON indicate all bit errors in the framing pattern or only one error for one or more errors in the framing pattern. When WORDERR is logic 1, the FERR indication to PMON pulses once per frame, accumulating one error for one or more framing bit errors occurred. When WORDERR is logic 0, the FERR indication to PMON pulses for each and every framing bit error that occurs; PMON accumulates all framing bit errors. WORDBIP: The WORDBIP bit selects whether the parity bit error indication pulses to the E3-TRAN block indicate all bit errors in the BIP-8 pattern or only one error for one or more errors in the BIP-8 pattern. When WORDBIP is logic 1, the parity error indication to the E3 TRAN block pulses once per frame, indicating that one or more parity bit errors occurred. When WORDBIP is logic 0, the parity error indication to the E3-TRAN block pulses for each and every parity bit error that occurs. For G.832 applications, this bit should be set to logic 1.
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Register 03AH, 13AH, 23AH, 33AH: E3 FRMR Framing Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOFE: The OOFE bit is an interrupt enable. When OOFE is logic 1, a change of state of the OOF status generates an interrupt and sets the INTB output to logic 0. When OOFE is logic 0, changes of state of the OOF status are disabled from causing interrupts on the INTB output. COFAE: The COFAE bit is an interrupt enable. When COFAE is logic 1, a change of frame alignment generates an interrupt and sets the INTB output to logic 0. When COFAE is logic 0, changes of frame alignment are disabled from causing interrupts on the INTB output. LCVE: The LCVE bit is an interrupt enable. When LCVE is logic 1, detection of a line code violation generates an interrupt and sets the INTB output to logic 0. When LCVE is logic 0, occurrences of line code violations are disabled from causing interrupts on the INTB output. LOSE: The LOSE bit is an interrupt enable. When LOSE is logic 1, a change of state of the loss-of-signal generates an interrupt and sets the INTB output to logic 0. When LOSE is logic 0, occurrences of loss-of-signal are disabled from causing interrupts on the INTB output. R/W R/W R/W R/W R/W Type Function Unused Unused Unused CZDE LOSE LCVE COFAE OOFE Default X X X 0 0 0 0 0
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CZDE: The CZDE bit is an interrupt enable. When CZDE is logic 1, detection of four consecutive zeros in the HDB3-encoded stream generates an interrupt and sets the INTB output to logic 0. When CZDE is logic 0, occurrences of consecutive zeros are disabled from causing interrupts on the INTB output.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 03BH, 13BH, 23BH, 33BH: E3 FRMR Framing Interrupt Indication and Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 OOF: The OOF bit indicates the current state of the E3-FRMR. When OOF is logic 1, the E3-FRMR is out of frame alignment and actively searching for the new alignment. While OOF is high all status indications and overhead extraction continue with the previous known alignment. When OOF is logic 0, the E3-FRMR has found a valid frame alignment and is operating in a maintenance mode, indicating framing bit errors, and extracting and processing overhead bits. During reset, OOF is set to logic 1, but the setting may change prior to the register being read. LOS: The LOS bit indicates the current state of the Loss-Of-Signal detector. When LOS is logic 1, the E3-FRMR has received 32 consecutive RCLK cycles with no occurrences of bipolar data on RPOS and RNEG. When LOS is logic 0, the FRMR is receiving valid bipolar data. When the E3-FRMR has declared loss of signal, the LOS indication is set to logic 0 (de-asserted) when the E3-FRMR has received 32 consecutive RCLK cycles containing no occurrences of 4 consecutive zeros. The LOS bit is forced to logic 0 if the UNI bit is logic 1. During reset, LOS is set to logic 0, but the setting may change prior to the register being read. OOFI: A logic 1 OOFI bit indicates a change in the OOF status. The OOFI bit is cleared to logic 0 upon the completion of the register read. When OOFI is R R R R R R R Type Function Unused CZDI LOSI LCVI COFAI OOFI LOS OOF Default X X X X X X X X
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logic 0, it indicates that no OOF state change has occurred since the last time this register was read. COFAI: The COFAI bit indicates that a change of frame alignment between the previous alignment and the newly found alignment has occurred. When COFAI is logic 1, the last high-to-low transition on the OOF signal resulted in the new frame alignment differing from the previous one. The COFAI bit is cleared to logic 0 upon the completion of the register read. When COFAI is logic 0, it indicates that no change in frame alignment has occurred when OOF went low. LCVI: The LCVI bit indicates that a line code violation has occurred. When LCVI is logic 1, a line code violation on the RPOS and RNEG inputs was detected since the last time this register was read. The LCVI bit is cleared to logic 0 upon the completion of the register read. When LCVI is logic 0, it indicates that no line code violation was detected since the last register read. When the UNI bit in the Framing Options register is logic 1, the LCVI is forced to logic 0. LOSI: The LOSI bit indicates that a state transition occurred on the LOS status signal. When LOSI is logic 1, a high-to-low or low-to-high transition occurred on the LOS status signal since the last time this register was read. The LOSI bit is cleared to logic 0 upon the completion of the register read. When LOSI is logic 0, it indicates that no state change has occurred on LOS since the last time this register was read. When the UNI bit in the Framing Options register is logic 1, the LOSI is forced to logic 0. CZDI: The CZDI bit indicates that four consecutive zeros in the HDB3-encoded stream have been detected. CZDI is asserted to a logic 1, whenever the CZD signal is asserted. The CZDI bit is cleared to a logic 0 upon the completion of the register read. When CZDI is logic 0, it indicates that no occurrences of four consecutive zeros was detected since the last register read. When the UNI bit in the Framing Options register is logic 1, the CZDI indication is forced to logic 0. The interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the state of the framer. The indication bits (bits 2,3,4,5,6 of this register) are cleared
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to logic 0 after the register is read; the INTB output is also cleared to logic 1 if the interrupt was generated by any of these five events.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 03CH, 13CH, 23CH, 33CH: E3 FRMR Maintenance Event Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NATUSEE: The NATUSEE bit is an interrupt enable. When NATUSEE is logic 1, an interrupt is generated on the INTB output when the National Use bit (bit 12 of the frame in G.751 E3 mode) changes state. When NATUSEE is logic 0, changes in state of the National Use bit does not cause an interrupt on INTB. TIMEMKE: The TIMEMKE bit is an interrupt enable. When TIMEMKE is logic 1, an interrupt is generated on the INTB output when the Timing Marker bit (bit 8 of the G.832 Maintenance and Adaptation byte) changes state after the selected persistency check is applied. When TIMEMKE is logic 0, changes in state of the Timing Marker bit does not cause an interrupt on INTB. PTYPEE: The PTYPEE bit is an interrupt enable. When PTYPEE is logic 1, an interrupt is generated on the INTB output when the Payload Type bits (bits 3,4,5 of the G.832 Maintenance and Adaptation byte) change state. When PTYPEE is logic 0, changes in state of the Payload Type bits does not cause an interrupt on INTB. FEBEE: The FEBEE bit is an interrupt enable. When FEBEE is logic 1, an interrupt is generated on the INTB output when the Far End Block Error indication bit (bit 2 of the G.832 Maintenance and Adaptation byte) changes state. When
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function FERRE PERRE AISDE FERFE FEBEE PTYPEE TIMEMKE NATUSEE
Default 0 0 0 0 0 0 0 0
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FEBEE is logic 0, changes in state of the FEBE bit does not cause an interrupt on INTB. FERFE: The FERFE bit is an interrupt enable. When FERFE is logic 1, an interrupt is generated on the INTB output when the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when the Remote Alarm indication bit (bit 11 of the frame in G.751) changes state after the selected persistency check is applied. When FERFE is logic 0, changes in state of the FERF or RAI bit does not cause an interrupt on INTB. AISDE: The AISDE bit is an interrupt enable. When AISDE is logic 1, an interrupt is generated on the INTB output when the AISD indication changes state. When AISDE is logic 0, changes in state of the AISD signal does not cause an interrupt on INTB. PERRE: The PERRE bit is an interrupt enable. When PERRE is logic 1, an interrupt is generated on the INTB output when a BIP-8 error (in G.832 mode) is detected. When PERRE is logic 0, occurrences of BIP-8 errors do not cause an interrupt on INTB. FERRE: The FERRE bit is an interrupt enable. When FERRE is logic 1, an interrupt is generated on the INTB output when a framing bit error is detected. When FERRE is logic 0, occurrences of framing bit errors do not cause an interrupt on INTB.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 03DH, 13DH, 23DH, 33DH: E3 FRMR Maintenance Event Interrupt Indication Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NATUSEI: The NATUSEI bit is a transition Indication. When NATUSEI is logic 1, a change of state of the National Use bit (bit 12 of the frame in G.751 E3 mode) has occurred. When NATUSEI is logic 0, no change of state of the National Use bit has occurred since the last time this register was read. TIMEMKI: The TIMEMKI bit is a transition indication. When TIMEMKI is logic 1, a change in state of the Timing Marker bit (bit 8 of the G.832 Maintenance and Adaptation byte) has occurred. When TIMEMKI is logic 0, no changes in the state of the Timing Marker bit occurred since the last time this register was read. PTYPEI: The PTYPEI bit is a transition indication. When PTYPEI is logic 1, a change of state of the Payload Type bits (bits 3,4,5 of the G.832 Maintenance and Adaptation byte) has occurred. When PTYPEI is logic 0, no changes in the state of the Payload Type bits has occurred since the last time this register was read. FEBEI: The FEBEI bit is a transition indication. When FEBEI is logic 1, a change of state of the Far End Block Error indication bit (bit 2 of the G.832 Maintenance and Adaptation byte) has occurred. When FEBEI is logic 0, no changes in
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Type R R R R R R R R
Function FERRI PERRI AISDI FERFI FEBEI PTYPEI TIMEMKI NATUSEI
Default 0 0 0 0 0 0 0 0
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the state of the FEBE bit has occurred since the last time this register was read. FERFI: The FERFI bit is a transition indication. When FERFI is logic 1, a change of state of the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or when the Remote Alarm indication bit (bit 12 of the frame in G.751) has occurred. When FERFI is logic 0, no changes in the state of the FERF or RAI bit has occurred since the last time this register was read. AISDI: The AISDI bit is a transition indication. When AISDI is logic 1, a change in state of the AISD indication has occurred. When AISDI is logic 0, no changes in the state of the AISD signal has occurred since the last time this register was read. PERRI: The PERRI bit is an event indication. When PERRI is logic 1, the occurrence of one or more BIP-8 errors (in G.832 mode) has been detected. When PERRI is logic 0, no occurrences of BIP-8 errors have occurred since the last time this register was read. FERRI: The FERRI bit is an event indication. When FERRI is logic 1, the occurrence of one or more framing bit error has been detected. When FERRI is logic 0, no occurrences of framing bit errors have occurred since the last time this register was read. The transition/event interrupt indications within this register work independently from the interrupt enable bits, allowing the microprocessor to poll the register to determine the activity of the maintenance events. The contents of this register are cleared to logic 0 after the register is read; the INTB output is also cleared to logic 1 if the interrupt was generated by any of the Maintenance Event outputs.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 03EH, 13EH, 23EH, 33EH: E3 FRMR Maintenance Event Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NATUSE: The NATUSE bit reflects the state of the extracted National Use bit (bit 12 of the frame in G.751 E3 mode). TIMEMK: The TIMEMK bit reflects the state of the Timing Marker bit (bit 8 of the G.832 Maintenance and Adaptation byte). PTYPE[2:0]: The PTYPE[2:0] bits reflect the state of the Payload Type bits (bits 3,4,5 of the G.832 Maintenance and Adaptation byte). These bits are not latched and should be read 2 or 3 times in rapid succession to ensure a coherent binary value. FEBE: The FEBE bit reflects the state of the Far End Block Error indication bit (bit 2 of the G.832 Maintenance and Adaptation byte). FERF: The FERF bit reflects the value of the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or the value of the Remote Alarm indication bit (bit 11 of the frame in G.751) when the value has been the same for either 3 or 5 consecutive frames. Type R R R R R R R R Function AISD FERF/RAI FEBE PTYPE[2] PTYPE[1] PTYPE[0] TIMEMK NATUSE Default X X X X X X X X
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AISD: The AISD bit reflects the state of the AIS detection circuitry. When AISD is logic 1, less than 8 zeros (in G.832 mode), or less than 5 zeros (in G.751 mode), were detected during one complete frame period while the FRMR is out of frame alignment. When AISD is logic 0, 8 or more zeros (in G.832 mode), or 5 or more zeros (in G.751 mode), were detected during one complete frame period, or the FRMR has found frame alignment.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 040H, 140H, 240H, 340H: E3 TRAN Framing Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W R/W R/W Type Function Unused Unused Reserved Reserved Reserved Reserved FORMAT[1] FORMAT[0] Default X X 0 0 0 0 0 0
FORMAT[1:0]: The FORMAT[1:0] bits determine the framing mode used for framing pattern when generating the formatted output data stream. The FORMAT[1:0] bits select one of two framing formats: Table 13 FORMAT[1] 0 0 1 1 Reserved: The Reserved bits must be programmed to logic 0 for correct operation. - E3 TRAN FORMAT[1:0] Configurations FORMAT[0] 0 1 0 1 Framing Format Selected G.751 E3 format G.832 E3 format Reserved Reserved
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Register 041H, 141H, 241H, 341H: E3 TRAN Status and Diagnostic Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 NATUSE: The NATUSE bit determines the default value of the National Use bit inserted into the G.751 E3 frame overhead. The value of the NATUSE bit is logically ORed with the bit collected once per frame from the internal HDLC transmitter (if TNETOP is set to logic 1). When TNETOP is logic 0, the NATUSE bit controls the value of the National Use bit. When NATUSE is logic 1, the National Use bit (bit 12 in G.751) is forced to logic 1 regardless of the bit input from the internal HDLC transmitter or the setting of TNETOP When . NATUSE is logic 0, the National Use bit is set to the value sampled from the internal HDLC transmitter if TNETOP is logic 0. Otherwise, the National Use bit will be set to logic 0. If the E3 TRAN is configured for G.832 mode, this bit is ignored. TAIS: The TAIS bit enables AIS signal transmission. When TAIS is logic 1, the all 1's AIS signal is transmitted. When TAIS is logic 0, the normal data is transmitted. Reserved: The Reserved bit must be programmed to logic 0 for proper operation. DLCV: The DLCV bit selects whether a line code violation is generated for diagnostic purposes. When DLCV changes from logic 0 to logic 1, single LCV is generated; in HDB3, the LCV is generated by causing a bipolar violation
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Type
Function Unused
Default X 0 0 0 0 0 0 1
R/W R/W R/W R/W R/W R/W R/W
PYLD&JUST CPERR DFERR DLCV Reserved TAIS NATUSE
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pulse of the same polarity to the previous bipolar violation. To generate another LCV, the DLCV register bit must be first be written to logic 0 and then to logic 1 again. DFERR: The DFERR bit selects whether the framing pattern is corrupted for diagnostic purposes. When DFERR is logic 1, the framing pattern inserted into the output data stream is inverted. When DFERR is logic 0, the unaltered framing pattern inserted into the output data stream. CPERR: The CPERR bit enables continuous generation of BIP-8 errors for diagnostic purposes. When CPERR is logic 1, the calculated BIP-8 value is continuously inverted according to the error mask specified by the BIP-8 Error Mask register and inserted into the G.832 EM byte. When CPERR is logic 0, the calculated BIP-8 value is altered only once, according to the error mask specified by the BIP-8 Error Mask register, and inserted into the EM byte. PYLD&JUST: The PYLD&JUST bit selects whether the justification service bits and the tributary justification bits in framing modes G.751 is indicated as overhead or payload. When PYLD&JUST is logic 1, the justification service bits and the tributary justification bits are indicated as payload. When PYLD&JUST is logic 0, the justification service and tributary justification bits are indicated as overhead. For G.751 ATM applications, this bit must be set to logic 1 for correct cell mapping.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 042H, 142H, 242H, 342H: E3 TRAN BIP-8 Error Mask Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MBIP[7:0]: The MBIP[7:0] bits act as an error mask to cause the transmitter to insert up to 8 BIP-8 errors. The contents of this register are XORed with the calculated BIP-8 byte and inserted into the G.832 EM byte of the frame. A logic 1 in any MBIP bit position causes that bit position in the EM byte to be inverted. Writing this register with a mask value causes that mask to be applied only once; if continuous BIP-8 errors are desired, the CPERR bit in the Status and Diagnostic Options register can be used. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MBIP[7] MBIP[6] MBIP[5] MBIP[4] MBIP[3] MBIP[2] MBIP[1] MBIP[0] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 043H, 143H, 243H, 343H: E3 TRAN Maintenance and Adaptation Options Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TIMEMK: The TIMEMK bit determines the state of the Timing Marker bit (bit 8 of the G.832 Maintenance and Adaptation byte). When TIMEMK is set to logic 1, the Timing Marker bit in the MA byte is set to logic 1. When TIMEMK is set to logic 0, the Timing Marker bit in the MA byte is set to logic 0. TUMFRM[1:0]: The TUMFRM[1:0] bits reflect the value to be inserted in the Tributary Unit Multiframe bits (bits 6, and 7 of the G.832 Maintenance and Adaptation byte). These bits are logically ORed with the TUMFRM[1:0] overhead signals from the TOH input before being inserted in the MA byte. PTYPE[2:0]: The PTYPE[2:0] bits reflect the value to be inserted in the Payload Type bits (bits 3,4,5 of the G.832 Maintenance and Adaptation byte). FEBE: The FEBE bit reflects the value to be inserted in the Far End Block Error indication bit (bit 2 of the G.832 Maintenance and Adaptation byte). The FEBE bit value is logically ORed with the FEBE indications generated by the FRMR for any detected BIP-8 errors. When the FEBE bit is logic 1, bit 2 of the G.832 MA byte is set to logic 1; when the FEBE bit is logic 0, any BIP-8 error indications from the FRMR causes bit 2 of the MA byte to be set to logic 1.
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function FERF/RAI FEBE PTYPE[2] PTYPE[1] PTYPE[0] TUMFRM[1] TUMFRM[0] TIMEMK
Default 0 0 0 0 0 0 0 0
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FERF/RAI: The FERF/RAI bit reflects the value to be inserted in the Far End Receive Failure indication bit (bit 1 of the G.832 Maintenance and Adaptation byte), or the value of the Remote Alarm indication bit (bit 11 of the frame in G.751). The FERF/RAI bit is logically ORed with the LOS, OOF, AIS, and LCD indications from the E3 FRMR and RXCP-50 when the LOSEN, OOFEN, AISEN, and LCDEN register bits (in the S/UNI-QJET Data Link and FERF/RAI Control register) are set to logic 1 respectively. When the OR of the two signals is logic 1, the FERF or RAI bit in the frame is set to logic 1; when neither signal is logic 1, the FERF or RAI bit is set to logic 0.
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Register 044H, 144H, 244H, 344H: J2-FRMR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UNI: When the UNI bit is set to logic 0, the J2-FRMR expects unipolar data on the RDATI input and line code violation indications on the RLCV input. When UNI is logic 0, the J2-FRMR expects bipolar B8ZS encoded data on the RPOS and RNEG inputs. When UNI is set to logic 1, then the LOS, LOSI, and EXZI indications cannot be used. REFRAME: Writing the REFRAME bit logic 1 forces the J2-FRMR to declare loss of frame, and begin searching for a new alignment. In order to force another reframe, REFRAME must be written with logic 0, and then logic 1 again. FLOCK: When the FLOCK bit is set to logic 1, the J2-FRMR is prevented from declaring Loss of Frame and searching for a new frame alignment due to framing-pattern errors. In this case, the J2-FRMR will only search for frame alignment when the REFRAME register bit transitions from logic 0 to logic 1. CRC_REFR When the CRC Reframe Enable bit is set to logic 1, an alternate framing algorithm is enabled, which uses the CRC-5 check to detect framing to a mimic pattern in the payload or signaling bits. The framer, once it has seen at least one correct framing pattern, begins looking for correct CRC-5s as well. If it observes three consecutive correct framing patterns, and two correct CRC-5 sequences, then frame is declared. Otherwise, a reframe is initiated.
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Type
Function Unused
Default X 0 0 0 0 0 1 1
R/W R/W R/W R/W R/W R/W R/W
UNI REFRAME FLOCK CRC_REFR SFRME LOSTHR[1] LOSTHR[0]
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When CRC_REFR is set to logic 0, the framing algorithm simply searches for three consecutive correct framing patterns. SFRME When the Single Framing Bit Error (SFRME) bit is set to logic 1, then the J2FRMR will indicate (to the PMON) a single framing error for every J2 multiframe which contains one or more framing errors. When the SFRME bit is set to logic 0, the J2-FRMR will identify every framing error to the PMON. LOSTHR[1:0] The Loss of Signal Threshold bits select the number of consecutive zeroes required before the J2-FRMR will declare Loss of Signal (LOS), and the number of bit periods without an occurrence of excess zeroes that must pass before the J2-FRMR will de-assert Loss of Signal. The thresholds are as follows: Table 14 LOSTHR[1] 0 0 1 1 - J2 FRMR LOS Threshold Configurations LOSTHR[0] 0 1 0 1 Threshold 15 31 63 255
Thus, if LOSTHR[1:0] = 11 binary, LOS will be declared after the 255th consecutive binary zero, and de-asserted when 255 bit periods have passed without an occurrence of a string of eight or more consecutive zeroes.
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Register 045H, 145H, 245H, 345H: J2-FRMR Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R Type R R Function LOS LOF Unused RAI RLOF Unused PHYAIS PLDAIS Default X X X X X X X X
LOS, LOF, RAI, RLOF, PHYAIS, PLDAIS These register bits reflect the current state of the Loss of Signal (LOS), Loss of Frame (LOF), Remote Alarm Indication (RAI), Remote Loss of Frame (RLOF, also known as the a-bit), Physical AIS (PHYAIS), and Payload AIS (PLDAIS) conditions.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 046H, 146H, 246H, 346H: J2-FRMR Alarm Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOSE When LOSE is logic 1, the J2-FRMR will generate an interrupt when the LOS condition changes state. Note that the LOS bit is not valid when the UNI bit is set in the J2-FRMR Configuration Register. LOFE When LOFE is logic 1, the J2-FRMR will generate an interrupt when LOF changes state. COFAE When COFAE is logic 1, the J2-FRMR will generate an interrupt when a change of frame alignment occurs. RAIE When RAIE is logic 1, the J2-FRMR will generate an interrupt when RAI changes state. RLOFE When RLOFE is logic 1, the J2-FRMR will generate an interrupt when RLOF changes state. RLOF_THR The RLOF Threshold bit determines the number of consecutive a-bits that are required for the state of RLOF to change. When RLOF_THR is logic 0, RLOF Type R/W R/W R/W R/W R/W R/W R/W R/W Function LOSE LOFE COFAE RAIE RLOFE RLOF_THR PHYAISE PLDAISE Default 0 0 0 0 0 1 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
is asserted when the a-bit has been logic 1 for three consecutive frames, and de-asserted when the a-bit has been logic 0 for three consecutive frames. When RLOF_THR is logic 1, RLOF is asserted when the a-bit has been logic 1 for five consecutive frames, and de-asserted when the a-bit has been logic 0 for five consecutive frames. The default setting is that five consecutive abits are required. PHYAISE When PHYAISE is logic 1, the J2-FRMR will generate an interrupt when a change is detected in the Physical AIS condition. PLDAISE When PLDAISE is logic 1, the J2-FRMR will generate an interrupt when a change is detected in the Payload AIS condition.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 047H, 147H, 247H, 347H: J2-FRMR Alarm Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LOSI The LOSI bit is set to logic 1 if a change occurs in the LOS condition. LOSI is cleared when this register is read. LOFI The LOFI bit is set to logic 1 if a change occurs in the state of LOF. LOFI is cleared when this register is read. COFAI The COFAI bit is set to logic 1 if a change in frame alignment occurs. COFAI is cleared when this register is read. RAII The RAII bit is set to logic 1 if a change in the value of RAI occurs. RAII is cleared when this register is read. RLOFI The RLOFI bit is set to logic 1 if a change in the value of RLOF occurs. RLOFI is cleared when this register is read. PHYAISI The PHYAISI bit is set to logic 1 if a change in the condition of PHYAIS occurs. PHYAISI is cleared when this register is read. R R Type R R R R R Function LOSI LOFI COFAI RAII RLOFI Unused PHYAISI PLDAISI Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PLDAISI The PLDAISI bit is set to logic 1 if a change in the condition of PLDAIS occurs. PLDAISI is cleared when this register is read.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 048H, 148H, 248H, 348H: J2-FRMR Error/Xbit Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRCEE When CRCEE is logic 1, the J2-FRMR will generate an interrupt if a multiframe fails its CRC-5 check. FRMEE When FRMEE is logic 1, the J2-FRMR will generate an interrupt upon the reception of an errored framing bit. BPVE When BPVE is logic 1, the J2-FRMR will generate an interrupt upon the reception of a bipolar violation which is not part of a valid B8ZS code (when UNI is set to logic 0 in the J2-FRMR Configuration Register) or on the reception of a logic 1 on RLCV (when UNI is set to logic 1). EXZE When EXZE is logic 1, the J2-FRMR will generate an interrupt upon the reception of a string of eight-or-more consecutive zeroes. EXZE has no effect when UNI is set to logic 1 in the J2-FRMR Configuration Register. XBITE When XBITE is logic 1, the J2-FRMR will generate an interrupt when any of the x-bits (X1, X2, X3) change state. Because the XBIT interrupt is generated when the x-bit indications change, the interrupt is debounced along with them via the XBIT_DEB and XBIT_THR bits. R/W R/W Type R/W R/W R/W R/W R/W Function CRCEE FRMEE BPVE EXZE XBITE Unused XBIT_DEB XBIT_THR Default 0 0 0 0 0 X 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
XBIT_DEB When XBIT_DEB is set to logic 0, the x-bit indications in the J2-FRMR Error/Xbit Interrupt Status Register reflect the most recent value of the x-bits. When XBIT_DEB is set to logic 1, the x-bit indications change value only when an x-bit has maintained its value for 3 or 5 consecutive multiframes, depending on the setting of XBIT_THR. XBIT_THR When XBIT_THR is set to logic 1, then XBIT_THR controls the debouncing threshold of the x-bit indications in the J2-FRMR Error/Xbit Interrupt Status Register. When XBIT_THR is logic 0, the threshold is set to 3 consecutive multiframes; when XBIT_THR is logic 1, the threshold is set to 5 consecutive multiframes.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 049H, 149H, 249H, 349H: J2-FRMR Error/Xbit Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CRCEI The CRCEI bit is set to logic 1 if a failed CRC-5 check occurs. CRCEI is cleared when this register is read. FRMEI The FRMEI bit is set to logic 1 if an errored framing bit occurs. FRMEI is cleared when this register is read. BPVI The BPVI bit is set to logic 1 if a bipolar violation that is not part of a valid B8ZS code occurs (when UNI is logic 0 in the J2-FRMR Configuration Register) or if a 0 to 1 transition is detected on RLCV (when UNI is logic 1). BPVI is cleared when this register is read. EXZI The EXZI bit is set to logic 1 upon reception of eight-or-more consecutive zeroes. EXZI remains logic 0 while UNI is set to logic 1 in the J2_FRMR Configuration Register. EXZI is cleared when this register is read. XBITI The XBITI bit is set to logic 1 if a change in the debounced (if XBIT_DEB is set to logic 1) x-bits (X1, X2, and X3) is detected. XBITI is cleared when this register is read. Type R R R R R R R R Function CRCEI FRMEI BPVI EXZI XBITI X3 X2 X1 Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
X1, X2, X3: The X1, X2, and X3 bits reflect the most recent (debounced if XBIT_DEB is set to logic 1) value of bits 785, 786, and 787 respectively of frame 3 of each multiframe. These bits are the spare or `x-bits'
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 04CH, 14CH, 24CH, 34CH: J2-TRAN Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RLOF: The RLOF bit controls the state of the A-bit. When RLOF is a logic 1, the Abit is also set to logic 1. When RLOF is a logic 0, the A-bit is set to logic 0. The A-bit in the transmit stream may also be set to logic 1 if an LOF condition in the J2 FRMR is detected and the RBLEN bit is logic 1 in the S/UNI-QJET Data Link and FERF/RAI Control register. X1SET: The X1SET bit controls the state of the X1 bit (bit 785 in the third frame of a J2 multiframe). When X1SET is a logic 1, the X1 bit is set to logic 1. When X1SET is a logic 0, the X1 bit is set to logic 0. X2SET: The X2SET bit controls the state of the X2 bit (bit 786 in the third frame of a J2 multiframe). When X2SET is a logic 1, the X2 bit is set to logic 1. When X2SET is a logic 0, the X2 bit is set to logic 0. X3SET: The X3SET bit controls the state of the X3 bit (bit 787 in the third frame of a J2 multiframe). When X3SET is a logic 1, the X3 bit is set to logic 1. When X3SET is a logic 0, the X3 bit is set to logic 0. Reserved: The reserved register bits should be set to logic 0 for proper operation. R/W R/W R/W R/W R/W R/W R/W Type Function Unused Reserved Reserved Reserved X3SET X2SET X1SET RLOF Default X 0 0 0 1 1 1 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 04DH, 14DH, 24DH, 34DH: J2-TRAN Diagnostic Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DFERR: The DFERR bit controls the insertion of framing alignment signal errors. When DFERR is set to logic 1, the framing alignment signal is inverted. When DFERR is set to logic 0, the framing alignment signal is not inverted. DBPV: The DBPV bit controls the insertion of single bipolar violations. When DBPV bit transitions from 0 to 1, a violation is generated by masking the first violation pulse of a B8ZS signature. To generate another violation, this bit must first be written to 0 and then to logic 1 again. When DBPV is a logic 0, no violation is generated. DLOS: When set to logic 1, the DLOS bit forces the unipolar and bipolar outputs of the J2 TRAN to be all zeros. When DLOS is logic 0, the outputs of the J2 TRAN operate normally. DCRC: When set to logic 1, a the CRC-5 check bits (e1-5) are inverted before transmission. DCRC inverts the e1-5 bits even if CDIS of the J2 TRAN Configuration register is set to logic 1. R/W R/W R/W R/W R/W R/W Type Function Unused Unused PLDAIS PHYAIS DCRC DLOS DBPV DFERR Default X X 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PHYAIS: When set to logic 1, PHYAIS will cause the J2 TRAN to transmit an all 1's Alarm Indication Signal (AIS). PLDAIS: When set to logic 1, PLDAIS will cause the J2 TRAN to insert all 1's in the payload data bits. When PLDAIS is a logic 0, data is processed normally through the J2 TRAN.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 04EH, 14EH, 24EH, 34EH: J2-TRAN TS97 Signaling Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TS97[1:8]: The TS97[1:8] bits control what is inserted into the J2 timeslot 97 bits. TS97[1] is the first bit of timeslot 97 transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function TS97[1] TS97[2] TS97[3] TS97[4] TS97[5] TS97[6] TS97[7] TS97[8] Default 1 1 1 1 1 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 04FH, 14FH, 24FH, 34FH: J2-TRAN TS98 Signaling Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TS98[1:8]: The TS98[1:8] bits control what is inserted into the J2 timeslot 98 bits. TS98[1] is the first bit of timeslot 98 transmitted. Type R/W R/W R/W R/W R/W R/W R/W R/W Function TS98[1] TS98[2] TS98[3] TS98[4] TS98[5] TS98[6] TS98[7] TS98[8] Default 1 1 1 1 1 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 050H, 150H, 250H,350H: RDLC Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EN: The EN bit controls the overall operation of the RDLC. When EN is set to logic 1, RDLC is enabled; when set to logic 0, RDLC is disabled. When RDLC is disabled, the RDLC FIFO buffer and interrupts are all cleared. When RDLC is enabled, it will immediately begin looking for flags. TR: Setting the terminate reception (TR) bit to logic 1 forces the RDLC to immediately terminate the reception of the current data frame, empty the RDLC FIFO buffer, clear the interrupts, and begin searching for a new flag sequence. The RDLC handles a terminate reception event in the same manner as it would the toggling of the EN bit from logic 1 to logic 0 and back to logic 1. Thus, the RDLC state machine will begin searching for flags. An interrupt will be generated when the first flag is detected. The TR bit will reset itself to logic 0 after the register write operation is completed and a rising and falling edge occurs on the internal datalink clock input. If the RDLC Configuration Register is read after this time, the TR bit value returned will be logic 0. MEN: Setting the Match Enable (MEN) bit to logic 1 enables the detection and storage in the RDLC FIFO of only those packets whose first data byte matches either of the bytes written to the Primary or Secondary Match Address Registers, or the universal all ones address. When the MEN bit is logic 0, all packets received are written into the RDLC FIFO. R/W R/W R/W R/W R/W Type Function Unused Unused Unused Reserved MEN MM TR EN Default X X X 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
MM: Setting the Match Mask (MM) bit to logic 1 ignores the PA[1:0] bits of the Primary Address Match Register, the SA[1:0] bits of the Secondary Address Match Register, and the two least significant bits of the universal all ones address when performing the address comparison. Reserved: This register bit should be set to logic 0 for proper operation.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 051H, 151H, 251H, 351H: RDLC Interrupt Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 INTC[6:0]: The INTC[6:0] bits control the assertion of FIFO fill level set point interrupts. The value of INTC[6:0] = `b0000000 sets the interrupt FIFO fill level to 128. INTE: The Interrupt Enable bit (INTE) must set to logic 1 to allow the internal interrupt status to be propagated to the INTB output. When the INTE bit is logic 0 the RDLC will not assert INTB. The contents of the Interrupt Control Register should only be changed when the EN bit in the RDLC Configuration Register is logic 0. This prevents any erroneous interrupt generation. Type R/W R/W R/W R/W R/W R/W R/W R/W Function INTE INTC[6] INTC[5] INTC[4] INTC[3] INTC[2] INTC[1] INTC[0] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 052H, 152H, 252H, 352H: RDLC Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function FE OVR COLS PKIN PBS[2] PBS[1] PBS[0] INTR Default X X X X X X X X
Consecutive reads of the RDLC Status and Data registers should not occur at rates greater than 1/10 that of the clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). INTR: The interrupt (INTR) bit reflects the status of the internal RDLC interrupt. If the INTE bit in the RDLC Interrupt Control Register is set to logic 1, a RDLC interrupt (INTR is a logic 1) will cause INTB to be asserted low. The INTR register bit will be set to logic 1 when one of the following conditions occurs: 1. the number of bytes specified in the RDLC Interrupt Control register have been received on the data link and written into the FIFO 2. RDLC FIFO buffer overrun has been detected 3. the last byte of a packet has been written into the RDLC FIFO 4. the last byte of an aborted packet has been written into the RDLC FIFO 5. transition of receiving all ones to receiving flags has been detected. PBS[2:0]: The packet byte status (PBS[2:0]) bits indicate the status of the data last read from the FIFO as indicated in the following table:
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 15 PBS[2:0] 000 001
- RDLC PBS[2:0] Data Status Data Status The data byte read from the FIFO is not special. The data byte read from the FIFO is the dummy byte that was written into the FIFO when the first HDLC flag sequence (01111110) was detected. This indicates that the data link became active. The data byte read from the FIFO is the dummy byte that was written into the FIFO when the HDLC abort sequence (01111111) was detected. This indicates that the data link became inactive. Unused. The data byte read from the FIFO is the last byte of a normally terminated packet with no CRC error and the packet received had an integer number of bytes. The data byte read from the FIFO must be discarded because there was a non-integer number of bytes in the packet. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error. The packet was received in error. The data byte read from the FIFO is the last byte of a normally terminated packet with a CRC error and a non-integer number of bytes. The packet was received in error.
010
011 100
101 110
111
PKIN: The Packet In (PKIN) bit is logic 1 when the last byte of a non-aborted packet is written into the FIFO. The PKIN bit is cleared to logic 0 after the RDLC Status Register is read. COLS: The Change of Link Status (COLS) bit is set to logic 1 if the RDLC has detected the HDLC flag sequence (01111110) or HDLC abort sequence (01111111) in the data. This indicates that there has been a change in the data link status. The COLS bit is cleared to logic 0 by reading this register or by clearing the EN bit in the RDLC Configuration Register. For each change in link status, a byte is written into the FIFO. If the COLS bit is found to be logic 1 then the RDLC FIFO must be read until empty. The status of the data
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
link is determined by the PBS[2:0] bits associated with the data read from the RDLC FIFO. OVR: The overrun (OVR) bit is set to logic 1 when data is written over unread data in the RDLC FIFO buffer. This bit is not reset to logic 0 until after the Status Register is read. While the OVR bit is logic 1, the RDLC and RDLC FIFO buffer are held in the reset state, causing the COLS and PKIN bits to be reset to logic 0. FE: The FIFO buffer empty (FE) bit is set to logic 1 when the last RDLC FIFO buffer entry is read. The FE bit goes to logic 0 when the FIFO is loaded with new data.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 053H, 153H, 253H, 353H: RDLC Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RD[7] RD[6] RD[5] RD[4] RD[3] RD[2] RD[1] RD[0] Default X X X X X X X X
Consecutive reads of the RDLC Status and Data registers should not occur at rates greater than 1/10 that of the clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). RD[7:0]: RD[7:0] contains the received data link information. RD[0] corresponds to the first received bit of the data link message. This register reads from the RDLC 128-byte FIFO buffer. If data is available, the FE bit in the FIFO Input Status Register is logic 0. When an overrun is detected, an interrupt is generated and the FIFO buffer is held cleared until the RDLC Status Register is read.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 054H, 154H, 254H, 354H: RDLC Primary Address Match Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PA[7:0]: The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. PA[0] corresponds to the first received bit of the data link message. The MM bit in the Configuration Register is used mask off PA[1:0] during the address comparison. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PA[7] PA[6] PA[5] PA[4] PA[3] PA[2] PA[1] PA[0] Default 1 1 1 1 1 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 055H, 155H, 255H, 355H: RDLC Secondary Address Match Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SA[7:0]: The first byte received after a flag character is compared against the contents of this register. If a match occurs, the packet data, including the matching first byte, is written into the FIFO. SA[0] corresponds to the first received bit data link message. The MM bit in the Configuration Register is used mask off SA[1:0] during the address comparison. Type R/W R/W R/W R/W R/W R/W R/W R/W Function SA[7] SA[6] SA[5] SA[4] SA[3] SA[2] SA[1] SA[0] Default 1 1 1 1 1 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 058H, 158H, 258H, 358H: TDPR Configuration Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W R/W Type R/W R/W R/W Function FLGSHARE FIFOCLR Reserved Unused EOM ABT CRC EN Default 1 0 0 X 0 0 1 0
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). EN: The EN bit enables the TDPR functions. When EN is set to logic 1, the TDPR is enabled and flag sequences are sent until data is written into the TDPR Transmit Data register. When the EN bit is set to logic 0, the TDPR is disabled and an all 1's Idle sequence is transmitted on the datalink. CRC: The CRC enable bit controls the generation of the CCITT_CRC frame check sequence (FCS). Setting the CRC bit to logic 1 enables the CCITT-CRC generator and appends the 16-bit FCS to the end of each message. When the CRC bit is set to logic 0, the FCS is not appended to the end of the message. The CRC type used is the CCITT-CRC with generator polynomial x16 + x12 + x5 + 1. The high order bit of the FCS word is transmitted first. ABT: The Abort (ABT) bit controls the sending of the 7 consecutive ones HDLC abort code. Setting the ABT bit to a logic 1 causes the 01111111 code (the 0 is transmitted first) to be transmitted after the current byte from the TDPR FIFO is transmitted. The TDPR FIFO is then reset. All data in the TDPR
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FIFO will be lost. Aborts are continuously sent and the FIFO is held in reset until this bit is reset to a logic 0. At least one Abort sequence will be sent when the ABT bit transitions from logic 0 to logic 1. EOM: The EOM bit indicates that the last byte of data written in the Transmit Data register is the end of the present data packet. If the CRC bit is set then the 16-bit FCS word is appended to the last data byte transmitted and a continuous stream of flags is generated. The EOM bit is automatically cleared upon a write to the TDPR Transmit Data register. Reserved: This bit should be set to logic 0 for proper operation.
FIFOCLR: The FIFOCLR bit resets the TDPR FIFO. When set to logic 1, FIFOCLR will cause the TDPR FIFO to be cleared. FLGSHARE: The FLGSHARE bit configures the TDPR to share the opening and closing flags between successive frames. If FLGSHARE is logic 1, then the opening and closing flags between successive frames are shared. If FLGSHARE is logic 0, then separate closing and opening flags are inserted between successive frames.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 059H, 159H, 259H, 359H: TDPR Upper Transmit Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UTHR[6:0]: The UTHR[6:0] bits define the TDPR FIFO fill level which will automatically cause the bytes stored in the TDPR FIFO to be transmitted. Once the fill level exceeds the UTHR[6:0] value, transmission will begin. Transmission will not stop until the last complete packet is transmitted and the TDPR FIFO fill level is below UTHR[6:0] + 1. The value of UTHR[6:0] must always be greater than the value of LINT[6:0] unless both values are equal to 00H. R/W R/W R/W R/W R/W R/W R/W Type Function Unused UTHR[6] UTHR[5] UTHR[4] UTHR[3] UTHR[2] UTHR[1] UTHR[0] Default X 1 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 05AH, 15AH, 25AH, 35AH: TDPR Lower Interrupt Threshold Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LINT[6:0]: The LINT[6:0] bits define the TDPR FIFO fill level which causes an internal interrupt (LFILLI) to be generated. Once the TDPR FIFO level decrements to empty or to a value less than LINT[6:0], LFILLI and BLFILL register bits will be set to logic 1. LFILLI will cause an interrupt on INTB if LFILLE is set to logic 1. The value of LINT[6:0] must always be less than the value of UTHR[6:0] unless both values are equal to 00H. R/W R/W R/W R/W R/W R/W R/W Type Function Unused LINT[6] LINT[5] LINT[4] LINT[3] LINT[2] LINT[1] LINT[0] Default X 0 0 0 0 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 05BH, 15BH, 25BH, 35BH: TDPR Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LFILLE: The LFILLE enables a transition to logic 1 on LFILLI to generate an interrupt on INTB. If LFILLE is a logic 1, a transition to logic 1 on LFILLI will generate an interrupt on INTB. If LFILLE is a logic 0, a transition to logic 1 on LFILLI will not generate an interrupt on INTB. UDRE: The UDRE enables a transition to logic 1 on UDRI to generate an interrupt on INTB. If UDRE is a logic 1, a transition to logic 1 on UDRI will generate an interrupt on INTB. If UDRE is a logic 0, a transition to logic 1 on UDRI will not generate an interrupt on INTB. OVRE: The OVRE enables a transition to logic 1 on OVRI to generate an interrupt on INTB. If OVRE is a logic 1, a transition to logic 1 on OVRI will generate an interrupt on INTB. If OVRE is a logic 0, a transition to logic 1 on OVRI will not generate an interrupt on INTB. FULLE: The FULLE enables a transition to logic 1 on FULLI to generate an interrupt on INTB. If FULLE is a logic 1, a transition to logic 1 on FULLI will generate an interrupt on INTB. If FULLE is a logic 0, a transition to logic 1 on FULLI will not generate an interrupt on INTB. R/W R/W R/W R/W R/W Type Function Unused Unused Unused Reserved FULLE OVRE UDRE LFILLE Default X X X 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Reserved: This bit should be set to logic 0 for proper operation.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 05CH, 15CH, 25CH, 35CH: TDPR Interrupt Status/UDR Clear Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R R R R R R R Type Function Unused FULL BLFILL Unused FULLI OVRI UDRI LFILLI Default X X X X X X X X
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). LFILLI: The LFILLI bit will transition to logic 1 when the TDPR FIFO level transitions to empty or falls below the value of LINT[6:0] programmed in the TDPR Lower Interrupt Threshold register. LFILLI will assert INTB if it is a logic 1 and LFILLE is programmed to logic 1. LFILLI is cleared when this register is read. UDRI: The UDRI bit will transition to 1 when the TDPR FIFO underruns. That is, the TDPR was in the process of transmitting a packet when it ran out of data to transmit. UDRI will assert INTB if it is a logic 1 and UDRE is programmed to logic 1. UDRI is cleared when this register is read. OVRI: The OVRI bit will transition to 1 when the TDPR FIFO overruns. That is, the TDPR FIFO was already full when another data byte was written to the TDPR Transmit Data register. OVRI will assert INTB if it is a logic 1 and OVRE is programmed to logic 1. OVRI is cleared when this register is read.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FULLI: The FULLI bit will transition to logic 1 when the TDPR FIFO is full. FULLI will assert INTB if it is a logic 1 and FULLE is programmed to logic 1. FULLI is cleared when this register is read. BLFILL: The BLFILL bit is set to logic 1 if the current FIFO fill level is below the LINT[7:0] level or is empty. FULL: The FULL bit reflects the current condition of the TDPR FIFO. If FULL is a logic 1, the TDPR FIFO already contains 128-bytes of data and can accept no more.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 05DH, 15DH, 25DH, 35DH: TDPR Transmit Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function TD[7] TD[6] TD[5] TD[4] TD[3] TD[2] TD[1] TD[0] Default X X X X X X X X
Consecutive writes to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register and reads of the TDPR Interrupt Status/UDR Clear register should not occur at rates greater than 1/8th that of the clock selected by the LINESYSCLK bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). TD[7:0]: The TD[7:0] bits contain the data to be transmitted on the data link. Data written to this register is serialized and transmitted (TD[0] is transmitted first).
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 060H, 160H, 260H, 360H: RXCP-50 Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 DISCOR: The DISCOR bit controls the HCS error correction algorithm. When DISCOR is a logic 0, the error correction algorithm is enabled, and single-bit errors detected in the cell header are corrected. When DISCOR is a logic 1, the error correction algorithm is disabled, and any error detected in the cell header is treated as an uncorrectable HCS error. HCSDQDB: The HCSDQDB bit enables HCS checking for either ATM type cells or DQDB type cells. When logic 0, ATM type cells are processed by checking all 4 octets in the header for HCS validation. When logic 1, DQDB cells are processed by checking only 3 of the header octets (octets 2, 3 and 4) for HCS validation. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to comparison. When HCSADD is a logic 1, the polynomial is added, and the resulting HCS is compared. When HCSADD is a logic 0, the polynomial is not added, and the unmodified HCS is compared. HDSCR: HDSCR enables the self-synchronous x43 + 1 descrambler to continue running through the bytes which should contain the ATM cell headers. When HDSCR is set to logic 0, the descrambling polynomial will function only over the ATM payload bytes. When HDSCR is set to logic 1, the descrambling
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Type R/W R/W
Function DDSCR HDSCR Unused Unused Unused
Default 0 0 X X X 1 0 0
R/W R/W R/W
HCSADD HCSDQDB DISCOR
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
polynomial will function over all bytes, including the 5 ATM header bytes. This function is available for use with PPP packets and flags which are scrambled at the source to prevent the generation of "killer" sequences. DDSCR: The DDSCR bit controls the descrambling of the cell payload with the polynomial x43 + 1. When DDSCR is set to logic 1, cell payload descrambling is disabled. When DDSCR is set to logic 0, payload descrambling is enabled.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 061H, 161H, 261H, 361H: RXCP-50 Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function CCDIS HCSPASS IDLEPASS IN52 ALIGN[1] ALIGN[0] HCSFTR[1] HCSFTR[0] Default 0 0 0 0 0 0 0 0
HCSFTR[1:0]: The HCS filter bits, HCSFTR[1:0] indicate the number of consecutive errorfree cells required, while in detection mode, before reverting back to correction mode. Table 16 - RXCP-50 HCS Filtering Configurations Cell Acceptance Threshold One ATM cell with correct HCS before resumption of cell acceptance. This cell is accepted. Two ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. Four ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted. Eight ATM cells with correct HCS before resumption of cell acceptance. The last cell is accepted.
HCSFTR[1:0] 00 01 10 11
ALIGN[1:0]: ALIGN[1:0] configures the RXCP-50 to perform cell delineation based on byte, nibble, or bit wide search algorithms when ATM Direct Mapping is used. Cell alignment is relative to overhead bits in the serial input data stream. The ALIGN[1:0] bits are valid only if ATM direct mapping is used - PLCP framing must be disabled. Recommended settings for DS3, E3, and J2 are shown.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 17 ALIGN[1:0] 00 01 10 11 IN52:
- RXCP-50 Cell Delination Algorithm Base Cell Delineation Algorithm base Bit Nibble (DS3) Byte (E3,J2, E1, T1) Unused
The IN52 bit defines the number of bytes contained in incoming cells. When IN52 is a logic '0', incoming cells are 53 bytes in length. When IN52 is a logic '1', incoming cells are 52 bytes in length. In order for ATM cell delineation to function properly, incoming cells must be 53 bytes in length including a valid HCS byte. The HCS byte can be stripped off on the Utopia side using the DS27_53 register bit. If the S/UNI QJET is operating in PPP mode, incoming "cells" may be composed of 52 or 53 bytes without an HCS byte. In this case, the CCDIS register bit should be set to disable cell delineation, and the DS27_53 register bit should be set so that it is consistent with IN52. IDLEPASS: The IDLEPASS bit controls the function of the Idle Cell filter. When IDLEPASS is written with a logic 0, all cells that match the Idle Cell Header Pattern and Idle Cell Header Mask are filtered out. When IDLEPASS is a logic 1, the Idle Cell Header Pattern and Mask registers are ignored. The default state of this bit and the bits in the Idle Cell Header Mask and Idle Cell Header Pattern Registers enable the dropping of idle cells. HCSPASS: The HCSPASS bit controls the dropping of cells based on the detection of an uncorrectable HCS error. When HCSPASS is a logic 0, cells containing an uncorrectable HCS error are dropped. When HCSPASS is a logic 1, cells are passed to the receive FIFO regardless of errors detected in the HCS. Additionally, the HCS verification finite state machine never exits the correction mode. Regardless of the programming of this bit, cells are always dropped while the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states unless the CCDIS bit in this register is set to logic 1.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
CCDIS: The CCDIS bit can be used to disable all cell filtering and cell delineation. All payload data read by the RXCP-50 is passed into its FIFO without the requirement of having to find cell delineation first. If PLCP framing is disabled, then alignment of the data read out of the ATM interface with respect to the line overhead is set by the ALIGN[1:0] bits of this register.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 062H, 162H, 262H, 362H: RXCP-50 FIFO/UTOPIA Control & Config Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four-cell receive FIFO. When FIFORST is set to logic 0, the FIFO operates normally. When FIFORST is set to logic 1, the FIFO is immediately emptied and further writes into the FIFO are ignored (no incoming ATM cells will be stored in the FIFO). The FIFO remains empty and continues to ignore writes until a logic 0 is written to FIFORST. See section 12.8 on resetting the receive and transmit FIFOs. RCALEVEL0: The RCALEVEL0 register bit selects the behavior of RCA and DRCA[x] when they de-assert (transition to logic 0 if RCAINV is logic 0, or transition to logic 1 if RCAINV is logic 1) as the receive FIFO empties. When RCALEVEL0 is set to logic 1, DRCA[x] and RCA indicates that the receive FIFO is empty. RCA (and DRCA[x]), if polled, will de-assert on the rising RFCLK edge after Payload byte 48 (ATM8=1) or Payload byte 24 (ATM8=0) is output. When RCALEVEL0 is set to logic 0, DRCA[x] and RCA, if polled, indicates that the receive FIFO is near empty. DRCA[x] and RCA, if polled, will deassert on the rising RFCLK edge after Payload byte 43 (ATM8=1) or Payload byte 19 (ATM8=0) is output. R/W R/W R/W Type R/W Function RXPTYP Unused RCAINV RCALEVEL0 Unused Unused Unused FIFORST Default 0 X 0 1 X X X 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
RCAINV: The RCAINV bit inverts the polarity of the DRCA[x] and RCA output signal. When RCAINV is a logic 1, the polarity of DRCA[x] and RCA is inverted (DRCA[x] and RCA at logic 0 means there is a receive cell available to be read). When RCAINV is a logic 0, the polarity of RCA and DRCA[x] is not inverted. RXPTYP: The RXPTYP bit selects even or odd parity for output RXPRTY. When set to logic 1, output RXPRTY is the even parity bit for outputs RDAT[15:0]. When RXPTYP is set to logic 0, RXPRTY is the odd parity bit for outputs RDAT[15:0].
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 063H, 163H, 263H, 363H: RXCP-50 Interrupt Enables and Counter Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDE: The LCDE bit enables the generation of an interrupt due to a change in the LCD state. When LCDE is set to logic 1, the interrupt is enabled. FOVRE: The FOVRE bit enables the generation of an interrupt due to a FIFO overrun error condition. When FOVRE is set to logic 1, the interrupt is enabled. HCSE: The HCSE bit enables the generation of an interrupt due to the detection of a corrected or an uncorrected HCS error. When HCSE is set to logic 1, the interrupt is enabled. OOCDE: The OOCDE bit enables the generation of an interrupt due to a change in cell delineation state. When OOCDE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the RXCP-50 Count registers. When XFERE is set to logic 1, the interrupt is enabled. R/W R/W R/W R/W R/W Type R R Function XFERI OVR Unused XFERE OOCDE HCSE FOVRE LCDE Default X X X 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
OVR: The OVR bit is the overrun status of the RXCP-50 Performance Monitoring Count registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the RXCP50 Count registers have been overwritten. OVR is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of RXCP-50 Performance Monitoring Count data has occurred. A logic 1 in this bit position indicates that the RXCP-50 Count registers have been updated. This update is initiated by writing to one of the RXCP-50 Count register locations or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register. XFERI is set to logic 0 when this register is read.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 064H, 164H, 264H, 364H: RXCP-50 Status/Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDI: The LCDI bit is set high when there is a change in the loss of cell delineation (LCD) state. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set to logic 1 when a FIFO overrun occurs. This bit is reset immediately after a read to this register. No further FIFO overrun indications will occur until the condition which caused the original overrun has cleared. In the case where continuous FIFO overruns are occurring, only a single overrun indication (FOVRI -> `1') will be recorded until the overruns cease. UHCSI: The UHCSI bit is set high when an uncorrected HCS error is detected. This bit is reset immediately after a read to this register. CHCSI: The CHCSI bit is set high when a corrected HCS error is detected. This bit is reset immediately after a read to this register. OOCDI: The OOCDI bit is set high when the RXCP-50 enters or exits the SYNC state. The OOCDV bit indicates whether the RXCP-50 is in the SYNC state or not. The OOCDI bit is reset immediately after a read to this register. R R R R R Type R R Function OOCDV LCDV Unused OOCDI CHCSI UHCSI FOVRI LCDI Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
LCDV: The LCDV bit gives the Loss of Cell Delineation state. When LCD is logic 1, an out of cell delineation (OCD) defect has persisted for the number of cells specified in the LCD Count Threshold register. When LCD is logic 0, no OCD has persisted for the number of cells specified in the LCD Count Threshold register. The cell time period can be varied by using the LCDC[7:0] register bits in the RXCP-50 LCD Count Threshold register. OOCDV: The OOCDV bit indicates the cell delineation state. When OOCDV is high, the cell delineation state machine is in the 'HUNT' or 'PRESYNC' states and is hunting for the cell boundaries. When OOCDV is low, the cell delineation state machine is in the 'SYNC' state and cells are passed through the receive FIFO.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 065H, 165H, 265H, 365H: RXCP-50 LCD Count Threshold (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 R/W R/W R/W Type Function Unused Unused Unused Unused Unused LCDC[10] LCDC[9] LCDC[8] Default X X X X X 0 0 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 066H, 166H, 266H, 366H: RXCP-50 LCD Count Threshold (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LCDC[10:0]: The LCDC[10:0] bits represent the number of consecutive cell periods the receive cell processor must be out of cell delineation before loss of cell delineation (LCD) is declared. Likewise, LCD is not de-asserted until receive cell processor is in cell delineation for the number of cell periods specified by LCDC[10:0]. The default value of LCD[10:0] is 360, which translates to the following integration periods: Type R/W R/W R/W R/W R/W R/W R/W R/W Function LCDC[7] LCDC[6] LCDC[5] LCDC[4] LCDC[3] LCDC[2] LCDC[1] LCDC[0] Default 0 1 1 0 1 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 18 Format
- RXCP-50 LCD Integration Periods Average cell period 9.59 s 10.42 s 12.46 s 13.89 s 12.50 s 69.01 s 276.00 s 300.00 us 220.83 s 237.50 s Default LCD integration period 3.45 ms 3.75 ms 4.49 ms 5.00 ms 4.50 ms 24.84 ms 99.40 ms 108.00 ms 79.50 ms 85.50 ms
DS3 Direct Mapping DS3 PLCP E3 G.751 Direct Mapping E3 G.751 PLCP E3 G.832 J2 Direct Mapping DS1 Direct Mapping DS1 PLCP E1 Direct Mapping E1 PLCP
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 067H, 167H, 267H, 367H: RXCP-50 Idle Cell Header Pattern Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 GFC[3:0]: The GFC[3:0] bits contain the pattern to match in the first, second, third, and fourth bits of the first octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register. The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. Note that an all-zeros pattern must be present in the VPI and VCI fields of the idle or unassigned cell. PTI[2:0]: The PTI[2:0] bits contain the pattern to match in the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell, in conjunction with the Idle Cell Header Mask Register. The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. CLP: The CLP bit contains the pattern to match in the eighth bit of the fourth octet of the 53-octet cell, in conjunction with the Match Header Mask Register. The IDLEPASS bit in the Configuration 2 Register must be set to logic zero to enable dropping of cells matching this pattern. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[3] PTI[2] PTI[1] CLP Default 0 0 0 0 0 0 0 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 068H, 168H, 268H, 368H: RXCP-50 Idle Cell Header Mask Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 MGFC[3:0]: The MGFC[3:0] bits contain the mask pattern for the first, second, third, and fourth bits of the first octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MPTI[3:0]: The MPTI[3:0] bits contain the mask pattern for the fifth, sixth, and seventh bits of the fourth octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in any bit position enables the corresponding bit in the pattern register to be compared. A logic zero causes the masking of the corresponding bit. MCLP: The CLP bit contains the mask pattern for the eighth bit of the fourth octet of the 53-octet cell. This mask is applied to the Idle Cell Header Pattern Register to select the bits included in the cell filter. A logic one in this bit position enables the MCLP bit in the pattern register to be compared. A logic zero causes the masking of the MCLP bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function MGFC[3] MGFC[2] MGFC[1] MGFC[0] MPTI[2] MPTI[1] MPTI[0] MCLP Default 1 1 1 1 1 1 1 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 069H, 169H, 269H, 369H: RXCP-50 Corrected HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CHCS[7:0]: The CHCS[7:0] bits indicate the number of corrected HCS error events that occurred during the last accumulation interval. The contents of these registers are valid after 24 RCLK periods containing cell header or payload data (line or PLCP overhead periods do not count) after a transfer is triggered by a write to one of RXCP-50's performance monitor counters (registers x69H - x71H) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Type R R R R R R R R Function CHCS[7] CHCS[6] CHCS[5] CHCS[4] CHCS[3] CHCS[2] CHCS[1] CHCS[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06AH, 16AH, 26AH, 36AH: RXCP-50 Uncorrected HCS Error Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 UHCS[7:0]: The UHCS[7:0] bits indicate the number of uncorrectable HCS error events that occurred during the last accumulation interval. The contents of these registers are valid after 24 RCLK periods containing cell header or payload data (line or PLCP overhead periods do not count) after a transfer is triggered by a write to one of RXCP-50's performance monitor counters (registers x69H - x71H) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). Type R R R R R R R R Function UHCS[7] UHCS[6] UHCS[5] UHCS[4] UHCS[3] UHCS[2] UHCS[1] UHCS[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06BH, 16BH, 26BH, 36BH: RXCP-50 Receive Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[7] RCELL[6] RCELL[5] RCELL[4] RCELL[3] RCELL[2] RCELL[1] RCELL[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06CH, 16CH, 26CH, 36CH: RXCP-50 Receive Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function RCELL[15] RCELL[14] RCELL[13] RCELL[12] RCELL[11] RCELL[10] RCELL[9] RCELL[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06DH, 16DH, 26DH, 36DH: RXCP-50 Receive Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RCELL[18:0]: The RCELL[18:0] bits indicate the number of cells received and written into the receive FIFO during the last accumulation interval. Cells received and filtered due to HCS errors or Idle cell matches are not counted. The counter should be polled every second to avoid saturation. The contents of these registers are valid after 24 RCLK periods containing cell header or payload data (line or PLCP overhead periods do not count) after a transfer is triggered by a write to one of RXCP-50's performance monitor counters (registers x69H - x71H) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). R R R Type Function Unused Unused Unused Unused Unused RCELL[18] RCELL[17] RCELL[16] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06EH, 16EH, 26EH, 36EH: RXCP-50 Idle Cell Counter (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ICELL[7] ICELL[6] ICELL[5] ICELL[4] ICELL[3] ICELL[2] ICELL[1] ICELL[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 06FH, 16FH, 26FH, 36FH: RXCP-50 Idle Cell Counter Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function ICELL[15] ICELL[14] ICELL[13] ICELL[12] ICELL[11] ICELL[10] ICELL[9] ICELL[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 070H, 170H, 270H, 370H: RXCP-50 Idle Cell Counter (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 ICELL[18:0]: The ICELL[18:0] bits indicate the number of idle cells received during the last accumulation interval. The counter should be polled every second to avoid saturation. The contents of these registers are valid after 24 RCLK periods containing cell header or payload data (line or PLCP overhead periods do not count) after a transfer is triggered by a write to one of RXCP-50's performance monitor counters (registers x69H - x71H) or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). R R R Type Function Unused Unused Unused Unused Unused ICELL[18] ICELL[17] ICELL[16] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 080H, 180H, 280H, 380H: TXCP-50 Configuration 1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FIFORST: The FIFORST bit is used to reset the four cell transmit FIFO. When FIFORST is set to logic zero, the FIFO operates normally. When FIFORST is set to logic one, the FIFO is immediately emptied and ignores writes. The FIFO remains empty and continues to ignore writes until a logic zero is written to FIFORST. Null/unassigned cells are transmitted until a subsequent cell is written to the FIFO. See section 12.8 on resetting the receive and transmit FIFOs. DSCR: The DSCR bit controls the scrambling of the cell payload. When DSCR is a logic one, cell payload scrambling is disabled. When DSCR is a logic zero, payload scrambling is enabled. In the case where HSCR is logic one, the payload will be scrambled (along with the header) regardless of the setting of the DSCR bit. HCSADD: The HCSADD bit controls the addition of the coset polynomial, x6+x4+x2+1, to the HCS octet prior to insertion in the synchronous payload envelope. When HCSADD is a logic one, the polynomial is added, and the resulting HCS is inserted. When HCSADD is a logic zero, the polynomial is not added, and the unmodified HCS is inserted. HCSADD takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO.
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Type R/W R/W R/W R/W R/W R/W R/W R/W
Function TPTYP TCALEVEL0 HSCR HCSDQDB HCSB HCSADD DSCR FIFORST
Default 0 0 0 0 0 1 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
HCSB: The active low HCSB bit enables the internal generation and insertion of the HCS octet into the transmit cell stream. When HCSB is logic zero, the HCS is generated and inserted internally. When the HCSB and DS27_53 register bits are logic one, the HCS octet read from the transmit FIFO is inserted transparently into the transmit cell stream, but the TXCP-50 will still generate and insert the HCS octet for idle cells. If HCSB is logic one and the 26 word data structure is selected (DS27_53 is logic 0), then no HCS octet is inserted in the transmit data stream. HCSDQDB: The HCSDQDB bit controls the cell header octets included in the HCS calculation. When a logic 1 is written to HCSDQDB, header octets, 2, 3, and 4 are included in the HCS calculation as required by IEEE-802.6 DQDB specification. When a logic 0 is written to HCSDQDB, all four header octets are included in the HCS calculation as required by the ATM Forum UNI specification and ITU-T Recommendation I.432. HSCR: The Header Scramble enable bit, HSCR, enables scrambling of the ATM five octet header along with the payload. When set to logic one, the ATM header and payload are both scrambled. When set to logic zero, the header is left unscrambled and payload scrambling is determined by the DSCR bit. TCALEVEL0: The active high TCA (and DTCA[x]) level 0 bit, TCALEVEL0 determines what output TCA (and DTCA[x]) indicates when it de-asserts (transitions to logic 0 if TCAINV is logic 0, or transitions to logic 1 if TCAINV is logic 1). When TCALEVEL0 is set to logic 1, TCA (and DTCA[x]) indicates that the transmit FIFO is full and can accept no more writes. DTCA[x] and TCA, if polled, will de-assert on the rising TFCLK edge when Payload byte 47 (ATM8=1) or Payload word 23 (ATM8=0) is sampled. When TCALEVEL0 is set to logic zero, TCA (and DTCA[x]) indicates that the transmit FIFO is near full. DTCA[x] and TCA, if polled, will de-assert on the rising TFCLK edge when Payload byte 43 (ATM8=1) or Payload word 19 (ATM8=0) is sampled. TPTYP: The TPTYP bit selects even or odd parity for input TPRTY. When set to logic one, input TPRTY is the even parity bit for the TDAT input bus. When set to
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
logic zero, input TPRTY is the odd parity bit for the TDAT input bus. When ATM8 is set to logic one, the input bus consists of TDAT[7:0]. When ATM8 is logic zero, the input bus consists of TDAT[15:0].
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 081H, 181H, 281H, 381H: TXCP-50 Configuration 2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 HCSCTLEB: The active low HCS control enable, HCSCTLEB bit enables the XORing of the HCS Control byte with the generated HCS. When set to logic zero, the HCS Control byte provided in the third word of the 27 word data structure is XORed with the generated HCS. When set to logic one, XORing is disabled and the HCS Control byte is ignored. DHCS: The DHCS bit controls the insertion of HCS errors for diagnostic purposes. When DHCS is set to logic one, the HCS octet is inverted prior to insertion in the synchronous payload envelope. DHCS takes effect unconditionally regardless of whether a null/unassigned cell is being transmitted or whether the HCS octet has been read from the FIFO. DHCS occurs after any error insertion caused by the Control Byte in the 27-word data structure. FIFODP[1:0]: The FIFODP[1:0] bits determine the transmit FIFO cell depth at which TCA and DTCA[x] de-assert. FIFO depth control may be important in systems where the cell latency through the TXCP-50 must be minimized. When the FIFO is filled to the specified depth, the transmit cell available signal, TCA (and DTCA[x]) is deasserted. Note that regardless of what fill level FIFODP[1:0] is set to, the transmit cell processor can store 4 complete cells. The selectable FIFO cell depths are shown below: R/W R/W R/W R/W R/W Type Function Unused Unused Unused TCAINV FIFODP[1] FIFODP[0] DHCS HCSCTLEB Default X X X 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Table 19
- TXCP-50 FIFO Depth Configurations FIFODP[0] 0 1 0 1 FIFO DEPTH 4 cells 3 cells 2 cells 1 cell
FIFODP[1] 0 0 1 1 TCAINV:
The TCAINV bit inverts the polarity of the TCA (and DTCA[x]) output signal. When TCAINV is a logic 1, the polarity of TCA (and DTCA[x]) is inverted (TCA (and DTCA[x]) at logic 0 means there is transmit cell space available to be written to). When TCAINV is a logic 0, the polarity of TCA (and DTCA[x]) is not inverted.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 082H, 182H, 282H, 382H: TXCP-50 Cell Count Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: These bits should be set to their default values for proper operation XFERI: The XFERI bit indicates that a transfer of Transmit Cell Count data has occurred. A logic 1 in this bit position indicates that the Transmit Cell Count registers have been updated. This update is initiated by writing to one of the Transmit Cell Count register locations or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register. XFERI is set to logic 0 when this register is read. OVR: The OVR bit is the overrun status of the Transmit Cell Count registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the Transmit Cell Count registers have been overwritten. OVR is set to logic 0 when this register is read. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the Transmit Cell Count registers. When XFERE is set to logic 1, the interrupt is enabled. R/W R/W R/W R/W Type R/W R R Function XFERE XFERI OVR Unused Reserved Reserved Reserved Reserved Default 0 X X X 1 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 083H, 183H, 283H, 383H: TXCP-50 Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TSOCI: The TSOCI bit is set high when the TSOC input is sampled high during any position other than the first word of the selected data structure. The write address counter is reset to the first word of the data structure when TSOC is sampled high. This bit is reset immediately after a read to this register. FOVRI: The FOVRI bit is set high when an attempt is made to write into the FIFO when it is already full. This bit is reset immediately after a read to this register TPRTYI: The TPRTYI bit indicates if a parity error was detected on the TDAT input bus. When logic one, the TPRTYI bit indicates a parity error over the active TDAT bus. The active TDAT bus is TDAT[15:0] when ATM8 is tied low and is TDAT[7:0] when ATM8 is tied high. This bit is cleared when this register is read. Odd or even parity is selected using the TPTYPE bit. TSOCE: The TSOCE bit enables the generation of an interrupt when the TSOC input is sampled high during any position other than the first word of the selected data structure. When TSOCE is set to logic one, the interrupt is enabled. R R R Type R/W R/W R/W Function TPRTYE FOVRE TSOCE Unused Unused TPRTYI FOVRI TSOCI Default 0 0 0 X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
FOVRE: The FOVRE bit enables the generation of an interrupt due to an attempt to write the FIFO when it is already full. When FOVRE is set to logic one, the interrupt is enabled. TPRTYE: The TPRTYE bit enables transmit parity interrupts. When set to logic one, parity errors are indicated on INT and TPRTYI. When set to logic zero, parity errors are indicated using bit TPRTYI but are not indicated on output INT.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 084H, 184H, 284H, 384H: TXCP-50 Idle Cell Header Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 CLP: The CLP bit contains the eighth bit position of the fourth octet of the idle/unassigned cell pattern. Cell rate decoupling is accomplished by transmitting idle cells when the TXCP-50 detects that no outstanding cells exist in the transmit FIFO. PTI[3:0]: The PTI[3:0] bits contains the fifth, sixth, and seventh bit positions of the fourth octet of the idle/unassigned cell pattern. Idle cells are transmitted when the TXCP-50 detects that no outstanding cells exist in the transmit FIFO. GFC[3:0]: The GFC[3:0] bits contain the first, second, third, and fourth bit positions of the first octet of the idle/unassigned cell pattern. Idle/unassigned cells are transmitted when the TXCP-50 detects that no outstanding cells exist in the transmit FIFO. The all zeros pattern is transmitted in the VCI and VPI fields of the idle cell. Type R/W R/W R/W R/W R/W R/W R/W R/W Function GFC[3] GFC[2] GFC[1] GFC[0] PTI[2] PTI[1] PTI[0] CLP Default 0 0 0 0 0 0 0 1
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 085H, 185H, 285H, 385H: TXCP-50 Idle Cell Payload Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PAYLD[7:0]: The PAYLD[7:0] bits contain the pattern inserted in the idle cell payload. Idle cells are inserted when the TXCP-50 detects that the transmit FIFO contains no outstanding cells. PAYLD[7] is the most significant bit and is the first bit transmitted. PAYLD[0] is the least significant bit. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PAYLD[7] PAYLD[6] PAYLD[5] PAYLD[4] PAYLD[3] PAYLD[2] PAYLD[1] PAYLD[0] Default 0 1 1 0 1 0 1 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 086H, 186H, 286H, 386H: TXCP-50 Transmit Cell Count (LSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[7] TCELL[6] TCELL[5] TCELL[4] TCELL[3] TCELL[2] TCELL[1] TCELL[0] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 087H, 187H, 287H, 387H: TXCP-50 Transmit Cell Count Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function TCELL[15] TCELL[14] TCELL[13] TCELL[12] TCELL[11] TCELL[10] TCELL[9] TCELL[8] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 088H, 188H, 288H, 388H: TXCP-50 Transmit Cell Count (MSB) Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 TCELL[18:0]: The TCELL[18:0] bits indicate the number of cells read from the transmit FIFO and inserted into the transmission stream during the last accumulation interval. Idle cells inserted into the transmission stream are not counted. A write to any one of the TXCP-50 Transmit Cell Counter registers or to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H) loads the registers with the current counter value and resets the internal 19 bit counter to 1 or 0. The counter reset value is dependent on if there was a count event during the transfer of the count to the Transmit Cell Counter registers. The counter should be polled every second to avoid saturating. The contents of these registers are valid after 24 TICLK periods containing cell header or payload data (line or PLCP overhead periods do not count) after a transfer is triggered by a write to a TXCP-50 Transmit Cell count Register or the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). R R R Type Function Unused Unused Unused Unused Unused TCELL[18] TCELL[17] TCELL[16] Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 090H, 190H, 290H, 390H: TTB Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Reserved: The reserved bit should be set to logic 0 for proper operation. NOSYNC: The NOSYNC bit disables synchronization to the Trail Trace message. When NOSYNC is set high, synchronization is disabled and the bytes of the Trail Trace message are captured by the TTB in a circular buffer. When NOSYNC is set low, the TTB synchronizes to the byte with the most significant bit set high and places that byte in the first location in the capture buffer page. TNULL: The transmit null (TNULL) bit controls the insertion of all-zeros into the outgoing Trail Trace message. The null insertion should be used when microprocessor accesses that change the outgoing trail trace message are being performed. When TNULL is set high, an all-zeros byte is inserted to the transmit stream. When this bit is set low, the contents of the transmit trace buffer are sent. PER5: The receive trace identifier persistency bit (PER5) controls the number of times that persistency check is made in order to accept the received message. When this bit is set high, five identical message required in order to accept the message. When this bit set low, three unchanged consecutive messages are required. Type R/W R/W R/W R/W R/W R/W R/W R/W Function ZEROEN RRAMACC RTIUIE RTIMIE PER5 TNULL NOSYNC Reserved Default 0 0 0 0 0 1 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
RTIMIE: The receive trace identifier mismatch interrupt enable (RTIMIE) controls the activation of the interrupt output when comparison between the accepted trace identifier message and the expected trace identifier message changes state from match to mismatch and vice versa. When RTIMIE is set high, changes in match state will activate the interrupt output. When RTIMIE set low, trail trace message match state changes will not affect INTB. RTIUIE: The receive trace identifier unstable interrupt enable (RTIUIE) control the activation of the interrupt output when the receive trace identifier message changes state from stable to unstable and vice versa. When RTIUIE is set high, changes in the state of the trail trace message unstable indication will activate the interrupt output. When RTIUIE set low, trail trace unstable state changes will not effect INTB. RRAMACC: The receive RAM access (RRAMACC) control bit is used by the microprocessor to identify that the access from the microprocessor is to the receive trace buffers (addresses 0 - 127) or to the transmit trace buffer (addresses 128 - 191). When RRAMACC is set high, subsequent microprocessor read and write accesses are directed to the receive side trace buffers. When RRAMACC is set low, microprocessor accesses are directed to the transmit side trace buffer. ZEROEN: The zero enable bit (ZEROEN) enables TIM assertion and removal based on an all ZEROs path trace message string. When ZEROEN is set high, all ZEROs path trace message strings are considered when entering and exiting TIM states. When ZEROEN is set low, all ZEROs path trace message strings are ignored.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 091H, 191H, 291H, 391H: TTB Trail Trace Identifier Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RTIMV: The receive trace identifier mismatch value status bit (RTIMV) is set high when the accepted message differs from the expected message. RTIMV is set low when the accepted message is equal to the expected message. A mismatch is not declared if the accepted trail trace message string is allzeros. RTIMI: The receive trace identifier mismatch indication status bit (RTIMI) is set high when match/mismatch status of the trace identifier framer changes state. This bit (and the interrupt) is cleared when this register is read. RTIUV: The receive trace identifier unstable value status bit (RTIUV) is set high when 8 messages that differ from its immediate predecessor are received. RTIUV is set low and the unstable message count is reset when 3 or 5 (depending on PER5 control bit) consecutive identical messages are received. RTIUI: The receive trace identifier unstable indication status bit (RTIUV) is set high when the stable/unstable status of the trace identifier framer changes state. This bit (and the interrupt) is cleared when this register is read. R R R R Type R Function BUSY Unused Unused Unused RTIUI RTIUV RTIMI RTIMV Default X X X X X X X X
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
BUSY: The BUSY bit reports whether a previously initiated indirect read or write to the trail trace RAM has been completed. BUSY is set high upon writing to the TTB Indirect Address register, and stays high until the access has completed. At this point, BUSY is set low. This register should be polled to determine when either new data is available in the TTB Indirect Data register after an indirect read, or when the TTB is ready to accept another write access.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 092H, 192H, 292H, 392H: TTB Indirect Address Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 A[6:0]: The indirect read address bits (A[6:0]) indexes into the trail trace identifier buffers. When RRAMACC is set high, decimal addresses 0 to 63 reference the receive capture page while addresses 64 to 127 reference the receive expected page. The receive capture page contains the identifier bytes extracted from the receive G.832 E3 stream. The receive expected page contains the expected trace identifier message down-loaded from the microprocessor. When RRAMACC is set low, decimal addresses 0 to 63 reference the transmit message buffer which contains the identifier message to be inserted in the TR bytes of the G.832 E3 transmit stream. In this case A[6] is a don't care (I.e., address 0 and address 64 are indexes to the same location in the buffer). Note that only the first 16 addresses need to be written with the trail trace message to be transmitted. RWB: The access control bit (RWB) selects between an indirect read or write access to the static page of the trail trace message buffer. Writing to this indirect address register initiates an external microprocessor access to the static page of the trail trace message buffer. When RWB is set high, a read access is initiated. The data read is available upon completion of the access in the TTB Indirect Data register. When RWB is set low, a write access is initiated. The data in the TTB Indirect Data register will be written to the addressed location in the static page. Type R/W R/W R/W R/W R/W R/W R/W R/W Function RWB A[6] A[5] A[4] A[3] A[2] A[1] A[0] Default 0 0 0 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 093H, 193H, 293H, 393H: TTB Indirect Data Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 D[7:0]: The indirect data bits (D[7:0]) contain either the data read from a message buffer after an indirect read operation has completed, or the data to be written to the RAM for an indirect write operation. Note that the write data must be set up in this register before an indirect write is initiated. Data read from this register reflects the value written until the completion of a subsequent indirect read operation. Type R/W R/W R/W R/W R/W R/W R/W R/W Function D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] Default X X X X X X X X
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 094H, 194H, 294H, 394H: TTB Expected Payload Type Label Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EXPLD[2:0]: The EXPLD[2:0] bits contain the expected payload type label bits of the G.832 E3 Maintenance and Adaptation (MA) byte. The EXPLD[2:0] bits are compared with the received payload type label extracted from the receive stream. A payload type label mismatch (PLDM) is declared if the received payload type bits differs from the expected payload type. If enabled, an interrupt is asserted upon declaration and removal of PLDM. For compatibility with old equipment that inserts 000B for unequipped or 001B for equipped, regardless of the payload type, the receive payload type label mismatch mechanism is based on the following table: Table 20 Expected 000 000 000 001 001 001 XXX - TTB Payload Type Match Configurations Received 000 001 XXX 000 001 XXX 000 Action Match Mismatch Mismatch Mismatch Match Match Mismatch Type R/W R/W R/W R/W R/W R/W R/W R/W Function Reserved Reserved Reserved Reserved Reserved EXPLD[2] EXPLD[1] EXPLD[0] Default 0 0 0 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Expected XXX XXX XXX Note:
Received 001 XXX YYY
Action Match Match Mismatch
XXX, YYY = anything except 000B or 001B, and XXX is not equal to YYY. Reserved: The reserved bits must be written to logic 0 for proper operation.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 095H, 195H, 295H, 395H: TTB Payload Type Label Control/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 RPLDMV: The receive payload type label mismatch status bit (RPLDMV) reports the match/mismatch status between the expected and the received payload type label. RPLDMV is set high when the received payload type bits differ from the expected payload type written to the TTB Expected Payload Type Label Register. The PLDMV bit is set low when the received payload type matches the expected payload type. RPLDMI: The receive payload type label mismatch interrupt status bit (RPLDMI) is set high when the match/mismatch status between the received and the expected payload type label changes state. This bit (and the interrupt) is cleared when this register is read. RPLDUV: The receive payload type label unstable status bit (RPLDUV) reports the stable/unstable status of the payload type label bits in the receive stream. RPLDUV is set high when 5 labels that differ from its immediate predecessor are received. RPLDUV is set low and the unstable label count is reset when 5 consecutive identical labels are received. RPLDUI: The receive payload type label unstable interrupt status bit (RPLDUI) is set high when the stable/unstable status of the path signal label changes state. This bit (and the interrupt) is cleared when this register is read.
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Type R/W R/W R R R R R R
Function RPLDUIE RPLDMIE Unused Unused RPLDUI RPLDUV RPLDMI RPLDMV
Default 0 0 X X X X X X
PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
RPLDMIE: The receive payload type label mismatch interrupt enable bit (RPLDMIE) controls the activation of the interrupt output when the comparison between received and the expected payload type label changes state from match to mismatch and vice versa. When RPLDMIE is set high, changes in match state activates the interrupt output. When RPLDMIE is set low, changes from match to mismatch or mismatch to match will not generate an interrupt. RPLDUIE: The receive payload type label unstable interrupt enable bit (RPLDUIE) controls the activation of the interrupt output when the received payload type label changes state from stable to unstable and vice versa. When RPLDUIE is set high, changes in stable state activates the interrupt output. When RPLDUIE is set low, changes in the stable state will not generate and interrupt.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 098H, 198H, 298H, 398H: RBOC Configuration/Interrupt Enable Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FEACE: The FEACE bit enables the generation of an interrupt when a valid far end alarm and control (FEAC) code is detected. When a logic 1 is written to FEACE, the interrupt generation is enabled. AVC: The AVC bit position selects the validation criterion used in determining a valid FEAC code. When a logic 0 is written to AVC, a FEAC code is validated when 8 out of the last 10 received codes are identical. The FEAC code is removed when 2 out of the last 10 received code do not match the validated code. When a logic 1 is written to AVC, a FEAC code is validated when 4 out of the last 5 received codes are identical. The FEAC code is removed when a single received FEACs does not match the validated code. IDLE: The IDLE bit enables the generation of an interrupt when a validated FEAC is removed. When a logic 1 is written to IDLE, the interrupt generation is enabled. R/W R/W R/W Type Function Unused Unused Unused Unused Unused IDLE AVC FEACE Default X X X X X 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 099H, 199H, 299H, 399H: RBOC Interrupt Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FEAC[5:0]: The FEAC[5:0] bits contain the received far end alarm and control channel codes. The FEAC[5:0] bits are set to all ones ("111111") when no code has been validated. FEACI: The FEACI bit is set to logic 1 when a new FEAC code is validated. The FEAC code value is contained in the FEAC[5:0] bits. The FEACI bit position is set to logic 0 when this register is read. IDLI: The IDLI bit is set to logic 1 when a validated FEAC code is removed. The FEAC[5:0] bits are set to all ones when the code is removed. The IDLI bit position is set to logic 0 when this register is read. Type R R R R R R R R Function IDLI FEACI FEAC[5] FEAC[4] FEAC[3] FEAC[2] FEAC[1] FEAC[0] Default X X X X X X X X
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 09AH, 19AH, 29AH, 39AH: XBOC Code Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FEAC[5:0]: FEAC[5:0] contain the six bit code that is transmitted on the far end alarm and control channel (FEAC). The transmitted code consists of a sixteen bit sequence that is repeated continuously. The sequence consists of 8 ones followed by a zero, followed by the six bit code sequence transmitted in order FEAC0, FEAC1, ..., FEAC5, followed by a zero. The all ones sequence is inserted in the FEAC channel when FEAC[5:0] is written with all ones. Note: If configured for J2 transmission format (TFRM[1:0] is 10 binary) and any of LCDEN, AISEN, OOFEN, LOSEN are set to logic 1 in the S/UNI-QJET Data Link and FERF/RAI Control, FEAC[5:0] in this register must all be set to logic 1 for proper RAI transmission upon detection of LCD, PHYAIS, LOF, or LOS by the J2 FRMR. Otherwise, the BOC code configured by the FEAC[5:0] bits of this register will be transmitted instead of the RAI. R/W R/W R/W R/W R/W R/W Type Function Unused Unused FEAC[5] FEAC[4] FEAC[3] FEAC[2] FEAC[1] FEAC[0] Default X X 1 1 1 1 1 1
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 09BH, 19BH, 29BH, 39BH: S/UNI-QJET Misc. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function AISOOF Reserved TPRBS Reserved TCELL LOC_RESET FORCELOS LINESYSCLK Default 0 0 0 0 0 0 0 0
LINESYSCLK: LINESYSCLK is used to select the high-speed system clock which the TDPR and RDLC transmit and receive HDLC controllers use as a reference. If LINESYSCLK is set to logic 1, then the RDLC uses the receive line clock (RCLK[x]) and the TDPR uses the transmit line clock (TICLK[x]) as its highspeed system reference clock respectively. If LINESYSCLK is set to logic 0, the RDLC uses the receive ATM Utopia interface clock (RFCLK) and the TDPR uses the transmit ATM Utopia interface clock (TFCLK) as its highspeed system reference clock respectively. The read/write access rate to the RDLC and TDPR are limited by their highspeed reference clock frequency. Data and Configuration settings can be written into the TDPR at a maximum rate equal to 1/8 of its high-speed reference clock frequency. Data and status indications can be read from the TDPR at a maximum rate equal to 1/8 of its high-speed reference clock frequency. Data and status indications can be read from the RDLC at a maximum rate equal to 1/10 of its high-speed reference clock frequency. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read and write the TDPR and RDLC registers. FORCELOS: FORCELOS is used to force a Loss of Signal (LOS) condition on the transmit unipolar or bipolar data outputs TPOS/TDATO[x] and TNEG[x]. When FORCELOS is logic 1, the TPOS/TDATO[x] and TNEG[x] outputs will be
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
forced to logic 0. When FORCELOS is logic 0, the TPOS/TDATO[x] and TNEG[x] outputs will operate normally. LOC_RESET: LOC_RESET performs a software local reset of the corresponding quadrant of the S/UNI-QJET. When LOC_RESET is logic 1, the corresponding quadrant of the S/UNI-QJET is held in a reset state. When LOC_RESET is logic 0, the quadrant is in normal operational mode. The LOC_RESET bit for quadrant 1 (reg 09BH) also resets the chip level Utopia bus. While the LOC_RESET for quadrant 1 is set to logic 1, the QJETs Utopia bus will be held in a reset state, and will not function. In applications where the Utopia bus is required, the LOC_RESET for quadrant 1 should not be permanently set to logic 1. TCELL: When the TCELL bit is a logic 1, the TPOHFP/TFPO/TMFPO/TGAPCLK/TCELL[4:1] pin takes on the TCELL function, and pulses once for every transmitted cell (idle or unassigned). Reserved: The reserved bit should be set to logic 0 for proper operation. TPRBS: Register bit TPRBS is used to insert a pseudo-random binary sequence into the transmit stream in place of other payload data. The exact nature of the PRBS is configurable through the PRGD registers (xA0H to xAFH). Reserved: The reserved bit should be set to logic 0 for proper operation. AISOOF: The AISOOF bit allows the receive data output stream on RDATO[x] to be forced to all 1's when the DS3, E3, or J2 FRMR loses frame. When AISOOF is set to logic 1, RDATO[x] will be forced to all 1's when frame alignment is lost. When AISOOF is set to logic 0, RDATO[x] will continue to output raw data even when frame alignment is lost. Note that AISOOF is only valid in framer-only mode (FRMRONLY=1, S/UNIQJET Configuration 1 register).
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 09CH, 19CH, 29CH, 39CH: S/UNI-QJET FRMR LOF Status. Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 FRMLOFI: The FRMLOFI bit shows that a transition has occurred on the FRMLOF state. When FRMLOFI is logic 1, the FRMLOF state has changed since the last read of this register. The FRMLOFI bit is cleared whenever this register is read. FRMLOFE: The FRMLOFE bit enables the generation of an interrupt due to a change in the FRMLOF state. When FRMLOFE is a logic 1, the interrupt is enabled. FRMLOF: The FRMLOF bit shows the current state of the E3/T3 LOF or the J2 Extended LOF indication (depending on which mode is enabled). When FRMLOF is logic 1, the framer has lost frame synchronization for greater than 1ms, 2ms, or 3ms depending on the setting of the LOFINT[1:0] bits in the S/UNI-QJET Receive Configuration register. Type R R/W R R/W R/W R/W R/W R/W Function FRMLOF FRMLOFE FRMLOFI J2SIGTHRU Reserved Reserved Reserved Reserved Default X 0 X 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
J2SIGTHRU: The J2SIGTHRU bit allows the signaling bits in timeslot 97 and 98 on the TDATI[x] stream to pass transparently through the J2 TRAN. When J2SIGTHRU is logic 1, timeslots 97 and 98 are passed transparently through from TDATI[x]. When J2SIGTHRU is logic 0, timeslots 97 and 98 are sourced from the J2 TRAN TS97 Signaling and J2 TRAN TS98 Signaling registers. If J2SIGTHRU is set to logic 1 and TPRBS (S/UNI-QJET Misc. register) is also set to logic 1, the transmitted PRBS will continue through timeslots 97 and 98. J2SIGTHRU is only valid in framer-only mode (FRMRONLY=1, S/UNI-QJET Configuration 1 register). Reserved: The reserved bits should be set to logic 0 for proper operation.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A0H, 1A0H, 2A0H, 3A0H: PRGD Control Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PDR[1:0]: The PDR[1:0] bits select the content of the four pattern detector registers (at addresses xACH to xAFH) to be any one of the pattern receive registers, the error count holding registers, or the bit count holding registers. The selection is shown in the following table: Table 21 PDR[1:0] 00, 01 - PRGD Pattern Detector Register Configuration PDR#1 Pattern Receive (LSB) Error Count (LSB) Bit Count (LSB) QRSS: The QRSS bit enables the zero suppression feature required when generating the QRSS sequence. When QRSS is a logic 1, a one is forced in the TDATO stream when the following 14 bit positions are all zeros. When QRSS is a logic 0, the zero suppression feature is disabled. PDR#2 Pattern Receive Error Count Bit Count Bit Count PDR#3 Pattern Receive Error Count PDR#4 Pattern Receive (MSB) Error Count (MSB) Bit Count (MSB) Type R/W R/W R/W R/W R/W R/W R/W R/W Function PDR[1] PDR[0] QRSS PS TINV RINV AUTOSYNC MANSYNC Default 0 0 0 0 0 0 1 0
10 11
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
PS: The PS bit selects the generated pattern. When PS is a logic 1, a repetitive pattern is generated. When PS is a logic 0, a pseudo-random pattern is generated. The PS bit must be programmed to the desired setting before programming any other PRGD registers, or the transmitted pattern may be corrupted. Any time the setting of the PS bit is changed, the rest of the PRGD registers should be reprogrammed. TINV: The TINV bit controls the logical inversion of the generated data stream. When TINV is a logic 1, the data is inverted. When TINV is a logic 0, the data is not inverted RINV: The RINV bit controls the logical inversion of the receive data stream before processing. When RINV is a logic 1, the received data is inverted before being processed by the pattern detector. When RINV is a logic 0, the received data is not inverted AUTOSYNC: The AUTOSYNC bit enables the automatic resynchronization of the pattern detector. The automatic resynchronization is activated when 6 or more bit errors are detected in the last 64 bit periods. When AUTOSYNC is a logic 1, the auto resync feature is enabled. When AUTO SYNC is a logic 0, the auto sync feature is disabled, and pattern resynchronization is accomplished using the MANSYNC bit. MANSYNC: The MANSYNC bit is used to initiate a manual resynchronization of the pattern detector. A low to high transition on MANSYNC initiates the resynchronization.
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A1H, 1A1H, 2A1H, 3A1H: PRGD Interrupt Enable/Status Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 SYNCE: The SYNCE bit enables the generation of an interrupt when the pattern detector changes synchronization state. When SYNCE is set to logic 1, the interrupt is enabled. BEE: The BEE bit enables the generation of an interrupt when a bit error is detected in the receive data. When BEE is set to logic 1, the interrupt is enabled. XFERE: The XFERE bit enables the generation of an interrupt when an accumulation interval is completed and new values are stored in the receive pattern registers, the bit counter holding registers, and the error counter holding registers. When XFERE is set to logic 1, the interrupt is enabled. SYNCV: The SYNCV bit indicates the synchronization state of the pattern detector. When SYNCV is a logic 1 the pattern detector is synchronized (the pattern detector has observed at least 32 consecutive error free bit periods). When SYNCV is a logic 0, the pattern detector is out of sync (the pattern detector has detected 6 or more bit errors in a 64 bit period window). Type R/W R/W R/W R R R R R Function SYNCE BEE XFERE SYNCV SYNCI BEI XFERI OVR Default 0 0 0 X X X X X
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
SYNCI: The SYNCI bit indicates that the detector has changed synchronization state since the last time this register was read. If SYNCI is logic 1, then the pattern detector has gained or lost synchronization at least once. SYNCI is set to logic 0 when this register is read. BEI: The BEI bit indicates that one or more bit errors have been detected since the last time this register was read. When BEI is set to logic 1, at least one bit error has been detected. BEI is set to logic 0 when this register is read. XFERI: The XFERI bit indicates that a transfer of pattern detector data has occurred. A logic 1 in this bit position indicates that the pattern receive registers, the bit counter holding registers and the error counter holding registers have been updated. This update is initiated by writing to one of the pattern detector register locations, or by writing to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H). XFERI is set to logic 0 when this register is read. OVR: The OVR bit is the overrun status of the pattern detector registers. A logic 1 in this bit position indicates that a previous transfer (indicated by XFERI being logic 1) has not been acknowledged before the next accumulation interval has occurred and that the contents of the pattern receive registers, the bit counter holding registers and the error counter holding registers have been overwritten. OVR is set to logic 0 when this register is read.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A2H, 1A2H, 2A2H, 3A2H: PRGD Length Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PL[4:0]: PL[4:0] determine the length of the generated pseudo random or repetitive pattern. The pattern length is equal to the value of PL[4:0] + 1. R/W R/W R/W R/W R/W Type Function Unused Unused Unused PL[4] PL[3] PL[2] PL[1] PL[0] Default X X X 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A3H, 1A3H, 2A3H, 3A3H: PRGD Tap Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PT[4:0]: PT[4:0] determine the feedback tap position of the generated pseudo random pattern. The feedback tap position is equal to the value of PT[4:0] + 1. R/W R/W R/W R/W R/W Type Function Unused Unused Unused PT[4] PT[3] PT[2] PT[1] PT[0] Default X X X 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A4H, 1A4H, 2A4H, 3A4H: PRGD Error Insertion Register Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 EVENT: A low to high transition on the EVENT bit causes a single bit error to be inserted in the generated pattern. This bit must be cleared and set again for a subsequent error to be inserted. EIR[2:0]: The EIR[2:0] bits control the insertion of a programmable bit error rate as indicated in the following table: Table 22 EIR[2:0] 000 001 010 011 100 101 110 111 - PRGD Generated Bit Error Rate Configurations Generated Bit Error Rate No errors inserted 10-1 10-2 10-3 10-4 10-5 10-6 10-7 R/W R/W R/W R/W Type Function Unused Unused Unused Unused EVENT EIR[2] EIR[1] EIR[0] Default X X X X 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A8H, 1A8H, 2A8H, 3A8H: Pattern Insertion #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[7] PI[6] PI[5] PI[4] PI[3] PI[2] PI[1] PI[0] Default 0 0 0 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0A9H, 1A9H, 2A9H, 3A9H: Pattern Insertion #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[15] PI[14] PI[13] PI[12] PI[11] PI[10] PI[9] PI[8] Default 0 0 0 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0AAH, 1AAH, 2AAH, 3AAH: Pattern Insertion #3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[23] PI[22] PI[21] PI[20] PI[19] PI[18] PI[17] PI[16] Default 0 0 0 0 0 0 0 0
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PM7346 S/UNI-QJET
DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0ABH, 1ABH, 2ABH, 3ABH: Pattern Insertion #4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PI[31:0]: PI[31:0] contain the data that is loaded in the pattern generator each time a new pattern (pseudo random or repetitive) is to be generated. When a pseudo random pattern is to be generated, PI[31:0] should be set to 0xFFFFFFFF. The data is loaded each time pattern insertion register #4 is written. Pattern insertion registers #1 - #3 should be loaded with the desired data before pattern register #4 is written. Type R/W R/W R/W R/W R/W R/W R/W R/W Function PI[31] PI[30] PI[29] PI[28] PI[27] PI[26] PI[25] PI[24] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0ACH, 1ACH, 2ACH, 3ACH: PRGD Pattern Detector #1 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[7] PD[6] PD[5] PD[4] PD[3] PD[2] PD[1] PD[0] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0ADH, 1ADH, 2ADH, 3ADH: PRGD Pattern Detector #2 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[15] PD[14] PD[13] PD[12] PD[11] PD[10] PD[9] PD[8] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0AEH, 1AEH, 2AEH, 3AEH: PRGD Pattern Detector #3 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Type R R R R R R R R Function PD[23] PD[22] PD[21] PD[20] PD[19] PD[18] PD[17] PD[16] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 0AFH, 1AFH, 2AFH, 3AFH: PRGD Pattern Detector #4 Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 PD[31:0]: PD[31:0] contain the pattern detector data. The values contained in these registers are determined by the PDR[1:0] bits in the control register. When PDR[1:0] is set to 00 or 01, PD[31:0] contain the pattern receive register. The 32 bits received immediately before the last accumulation interval are present on PD[31:0}. PD[31] contains the first of the 32 received bits, PD[0] contains the last of the 32 received bits. When PDR[1:0] is set to 10, PD[31:0] contain the error counter holding register. The value in this register represents the number of bit errors that have been accumulated since the last accumulation interval. Note that bit errors are not accumulated while the pattern detector is out of sync. When PDR[1:0] is set to 11, PD[31:0] contain the bit counter holding register. The value in this register represents the total number of bits that have been received since the last accumulation interval. The values of PD[31:0] are updated whenever one of the four PRGD Pattern Detector registers is written or when register 006H, the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register is written. Type R R R R R R R R Function PD[31] PD[30] PD[29] PD[28] PD[27] PD[26] PD[25] PD[24] Default 0 0 0 0 0 0 0 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
11
TEST FEATURES DESCRIPTION Simultaneously asserting (low) the CSB, RDB and WRB inputs causes all digital output pins and the data bus to be held in a high-impedance state. This test feature may be used for board testing. Test mode registers are used to apply test vectors during production testing of the S/UNI-QJET. Test mode registers (as opposed to normal mode registers) are selected when A[10] is high. Test mode registers may also be used for board testing. When all of the TSBs within the S/UNI-QJET are placed in test mode 0, device inputs may be read and device outputs may be forced via the microprocessor interface (refer to the section "Test Mode 0" for details). In addition, the S/UNI-QJET also supports a standard IEEE 1149.1 five-signal JTAG boundary scan test port for use in board testing. All digital device inputs may be read and all digital device outputs may be forced via the JTAG test port. Table 23 - Test Mode Register Memory Map Address 000H-3FFH 400H 408H 409H 40AH 40BH 40CH 40DH 40EH 40FH 410H 411H 412H41FH 508H 509H 50AH 50BH 50CH 50DH 50EH 50FH 510H 511H 512H51FH 608H 609H 60AH 60BH 60CH 60DH 60EH 60FH 610H 611H 612H61FH 708H 709H 70AH 70BH 70CH 70DH 70EH 70FH 710H 711H 712H71FH Register Normal Mode Registers Master Test Register SPLR Test Register 0 SPLR Test Register 1 SPLR Test Register 2 Reserved SPLT Test Register 0 SPLT Test Register 1 SPLT Test Register 2 SPLT Test Register 3 PMON Test Register 0 PMON Test Register 1 Reserved
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Address 420H 421H 422H 423H42FH 430H 431H 432H 433H 434H 435H 436H 437H 438H 439H 43AH 43BH43FH 440H 441H 442H 443H 444H 445H 446H 447H 448H44BH 44CH 520H 521H 522H 523H52FH 530H 531H 532H 533H 534H 535H 536H 537H 538H 539H 53AH 53BH53FH 540H 541H 542H 543H 544H 545H 546H 547H 548H54BH 54CH 620H 621H 622H 623H62FH 630H 631H 632H 633H 634H 635H 636H 637H 638H 639H 63AH 63BH63FH 640H 641H 642H 643H 644H 645H 646H 647H 648H64BH 64CH 720H 721H 722H 723H72FH 730H 731H 732H 733H 734H 735H 736H 737H 738H 739H 73AH 73BH73FH 740H 741H 742H 743H 744H 745H 746H 747H 748H74BH 74CH
Register CPPM Test Register 0 CPPM Test Register 1 CPPM Test Register 2 Reserved DS3 FRMR Test Register 0 DS3 FRMR Test Register 1 DS3 FRMR Test Register 2 DS3 FRMR Test Register 3 DS3 TRAN Test Register 0 DS3 TRAN Test Register 1 DS3 TRAN Test Register 2 Reserved E3 FRMR Test Register 0 E3 FRMR Test Register 1 E3 FRMR Test Register 2 Reserved E3 TRAN Test Register 0 E3 TRAN Test Register 1 E3 TRAN Test Register 2 Reserved J2 FRMR Test Register 0 J2 FRMR Test Register 1 J2 FRMR Test Register 2 J2 FRMR Test Register 3 Reserved J2 TRAN Test Register 0
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Address 44DH 44EH 44FH 450H 451H 452H 453H 454H 455H457H 458H 459H 45AH 45BH 45CH45FH 460H 461H 462H 463H 464H 465H 466H47FH 480H 481H 482H 483H 484H 54DH 54EH 54FH 550H 551H 552H 553H 554H 555H557H 558H 559H 55AH 55BH 55CH55FH 560H 561H 562H 563H 564H 565H 566H57FH 580H 581H 582H 583H 584H 64DH 64EH 64FH 650H 651H 652H 653H 654H 655H657H 658H 659H 65AH 65BH 65CH65FH 660H 661H 662H 663H 664H 665H 666H67FH 680H 681H 682H 683H 684H 74DH 74EH 74FH 750H 751H 752H 753H 754H 755H757H 758H 759H 75AH 75BH 75CH75FH 760H 761H 762H 763H 764H 765H 766H77FH 780H 781H 782H 783H 784H
Register J2 TRAN Test Register 1 J2 TRAN Test Register 2 J2 TRAN Test Register 3 RDLC Test Register 0 RDLC Test Register 1 RDLC Test Register 2 RDLC Test Register 3 RDLC Test Register 4 Reserved TDPR Test Register 0 TDPR Test Register 1 TDPR Test Register 2 TDPR Test Register 3 Reserved RXCP-50 Test Register 0 RXCP-50 Test Register 1 RXCP-50 Test Register 2 RXCP-50 Test Register 3 RXCP-50 Test Register 4 RXCP-50 Test Register 5 Reserved TXCP-50 Test Register 0 TXCP-50 Test Register 1 TXCP-50 Test Register 2 TXCP-50 Test Register 3 TXCP-50 Test Register 4
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Address 485H 486H48FH 490H 491H 492H 493H497H 498H 499H 49AH 49BH 49CH49FH 4A0H 4A1H 4A2H 4A3H 4A4H4FFH 585H 586H58FH 590H 591H 592H 593H597H 598H 599H 59AH 59BH 59CH59FH 5A0H 5A1H 5A2H 5A3H 5A4H5FFH 685H 686H68FH 690H 691H 692H 693H697H 698H 699H 69AH 69BH 69CH69FH 6A0H 6A1H 6A2H 6A3H 6A4H6FFH 785H 786H78FH 790H 791H 792H 793H797H 798H 799H 79AH 79BH 79CH79FH 7A0H 7A1H 7A2H 7A3H 7A4H7FFH
Register TXCP-50 Test Register 5 Reserved TTB Test Register 0 TTB Test Register 1 TTB Test Register 2 Reserved RBOC Test Register 0 RBOC Test Register 1 XBOC Test Register 1 XBOC Test Register 0 Reserved PRGD Test Register 0 PRGD Test Register 1 PRGD Test Register 2 PRGD Test Register 3 Reserved
Notes on Test Mode Register Bits: 1. Writing values into unused register bits has no effect. However, to ensure software compatibility with future, feature-enhanced versions of the product, unused register bits must be written with logic zero. Reading back unused bits can produce either a logic one or a logic zero; hence, unused register bits should be masked off by software when read. 2. Writable test mode register bits are not initialized upon reset unless otherwise noted.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Register 400H: S/UNI-QJET Master Test Bit Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 W W W W R/W W R/W Type Function Unused A_TM[9] A_TM[8] PMCTST DBCTRL IOTST HIZDATA HIZIO Default X X X X 0 0 0 0
This register is used to enable S/UNI-QJET test features. All bits, except PMCTST and A_TM[9:8], are reset to zero by a hardware reset of the S/UNI-QJET. The S/UNI-QJET Master Test register is not affected by a software reset (via the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register (006H)). HIZIO, HIZDATA: The HIZIO and HIZDATA bits control the tri-state modes of the S/UNI-QJET . While the HIZIO bit is a logic one, all output pins of the S/UNI-QJET except the data bus and output TDO are held tri-state. The microprocessor interface is still active. While the HIZDATA bit is a logic one, the data bus is also held in a high-impedance state which inhibits microprocessor read cycles. The HIZDATA bit is overridden by the DBCTRL bit. IOTST: The IOTST bit is used to allow normal microprocessor access to the test registers and control the test mode in each TSB block in the S/UNI-QJET for board level testing. When IOTST is a logic one, all blocks are held in test mode and the microprocessor may write to a block's test mode 0 registers to manipulate the outputs of the block and consequentially the device outputs (refer to the "Test Mode 0 Details" in the "Test Features" section). DBCTRL: The DBCTRL bit is used to pass control of the data bus drivers to the CSB pin. When the DBCTRL bit is set to logic one and either IOTST or PMCTST
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
are logic one, the CSB pin controls the output enable for the data bus. While the DBCTRL bit is set, holding the CSB pin high causes the S/UNI-QJET to drive the data bus and holding the CSB pin low tri-states the data bus. The DBCTRL bit overrides the HIZDATA bit. The DBCTRL bit is used to measure the drive capability of the data bus driver pads. PMCTST: The PMCTST bit is used to configure the S/UNI-QJET for PMC's manufacturing tests. When PMCTST is set to logic one, the S/UNI-QJET microprocessor port becomes the test access port used to run the PMC manufacturing test vectors. The PMCTST bit is logically "ORed" with the IOTST bit, and can be cleared by setting CSB to logic one or by writing logic zero to the bit. A_TM[9:8]: The state of the A_TM[9:8] bits internally replace the input address lines A[9:8] respectively when PMCTST is set to logic 1. This allows for more efficient use of the PMC manufacturing test vectors. 11.1 Test Mode 0 Details In test mode 0, the S/UNI-QJET allows the logic levels on the device inputs to be read through the microprocessor interface and allows the device outputs to be forced to either logic level through the microprocessor interface. The IOTST bit in the S/UNI-QJET Master Test register must be set to logic one to access the device I/O. To enable test mode 0, the IOTST bit in the S/UNI-QJET Master Test register is set to logic one and the device should be left in its default state after reset unless otherwise noted. All Test Register 1 locations of all blocks must be written with the value 0 (see Table 23). Reading the following address locations returns the values on the indicated inputs: Table 24
Addr 40CH 430H 436H 444H RPOS[1] RNEG[1] TOH[1] Bit 7
- Test Mode 0 Input Read Address Locations
Bit 6 TIOHM[1] Bit 5 TICLK[1] Bit 4 TPOH[1] Bit 3 TPOHINS[1] RCLK[1] TOHINS[1] Bit 2 Bit 1 Bit 0
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Addr 465H 466H 480H 482H 483H 484H 485H 50CH 50FH 530H 536H 544H 565H 60CH 630H 636H 644H 665H 70CH 730H 736H 744H 765H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1 RENB
3
Bit 0
RADR[4]
4
RADR[3]
4
RADR[2]
4
RADR[1] ATM8
4
RADR[0]
4
RFCLK
PHY_ADR[2] PHY_ADR[1] TDAT[15] TDAT[7]
TADR[4]
1
TSOC TADR[3] TDAT[13] TDAT[5] TICLK[2] TDAT[12] TDAT[4] TPOH[2]
1
TENB
2
TPRTY
1
TFCLK
1
PHY_ADR[0] TDAT[14] TDAT[6] TIOHM[2]
TADR[2]
TADR[1] TDAT[9] TDAT[1]
TADR[0] TDAT[8] TDAT[0]
1
TDAT[11] TDAT[3] TPOHINS[2]
TDAT[10] TDAT[2]
REF8KI RCLK[2] TOH[2] RPOS[2] RNEG[2] RADR[1]4 TIOHM[3] TICLK[3] TPOH[3] TPOHINS[3] RCLK[3] TOH[3] RPOS[3] RNEG[3] RADR[2] TIOHM[4] TICLK[4] TPOH[4] TPOHINS[4] RCLK[4] TOH[4] RPOS[4] RNEG[4] RADR[3]
4 4
TOHINS[2]
TOHINS[3]
TOHINS[4]
1. Before reading these values, the input must be set to the test state, TENB must be set to logic 1, and TFCLK must transition from logic 0 to logic 1. 2. TENB must be set to its test state and TFCLK must transition from logic 0 to logic 1 before its value will be captured in the test register. 3. RENB must be set to its test state and RFCLK must transition from logic 0 to logic 1 before its value will be captured in the test register. 4. Before reading these values, the input must be set to the test state, RENB must be set to logic 1, and RFCLK must transition from logic 0 to logic 1.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
Writing the following address locations forces the outputs to the value in the corresponding bit position (zeros should be written to all unused test register locations): Table 25
Addr 408H 40AH 40CH FRMSTAT[1] TPOHFP[1] TPOHCLK[ 1] 410H 430H 434H 436H 432H 433H 44CH 44EH 450H 458H 463H 464H 465H 480H RDAT[15] RDAT[7]
2 2 1
- Test Mode 0 Output Write Address Locations
Bit 6 Bit 5 Bit 4 Bit 3 RPOHCLK[1] Bit 2 RPOH[1] Bit 1 REF8KO[1] INTB
1
Bit 7
Bit 0
INTB INTB
1
TCLK[1] TOHFP[1] ROH[1] ROHFP[1] TPOS[1] TNEG[1] INTB INTB RDAT[14] RDAT[6] LCD[1]
2 2 1
TOHCLK[1] ROHCLK[1]
1
RDAT[13] RDAT[5] RSOC
2 2
2
RDAT[12] RDAT[4] RPRTY
2
2
RDAT[11] RDAT[3] RCA
3 2
2
RDAT[10] RDAT[2]
2
2
RDAT[9] RDAT[1] INTB
1
2
RDAT[8] RDAT[0]
2
2
2
2
DRCA[1] TCA , DTCA[1]
5 4,5
INTB
1
490H 498H 4A2H 508H 50AH 50CH FRMSTAT[2] TPOHFP[2] TPOHCLK[ 2] 510H 530H 534H 536H TOHFP[2] INTB
1
INTB INTB
1
1
INTB RPOHCLK[2] RPOH[2]
1
REF8KO[2] INTB
1
INTB
1
TCLK[2] TOHCLK[2]
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Addr 532H 533H 54CH 54EH 550H 558H 565H 580H 590H 598H 5A2H 608H 60AH 60CH
Bit 7
Bit 6
Bit 5 ROH[2]
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 ROHCLK[2]
ROHFP[2] TPOS[2] TNEG[2] INTB INTB LCD[2] RSOC
2 1
1
RPRTY
2
DRCA[2] DTCA[2]
5
INTB
1
INTB INTB
1
1
INTB
1
INTB RPOHCLK[3] FRMSTAT[3] TPOHFP[3] RPOH[3]
1
REF8KO[3] INTB TPOHCLK[ 3]
1 1
610H 630H 634H 636H 632H 633H 64CH 64EH 650H 658H 665H 680H 690H 698H 6A2H 708H 70AH 70CH FRMSTAT[4] TPOHFP[4] TPOHCLK[ 4] RPOHCLK[4] RPOH[4] INTB
1
INTB INTB
1
TCLK[3] TOHFP[3] ROH[3] ROHFP[3] TPOS[3] TNEG[3] INTB INTB LCD[3] RSOC
2 1
TOHCLK[3] ROHCLK[3]
1
RPRTY
2
DRCA[3] DTCA[3]
5
INTB
1
INTB INTB
1
1
INTB
1
REF8KO[4] INTB
1
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Addr 710H 730H 734H 736H 732H 733H 74CH 74EH 750H 758H 765H 780H 790H 798H 7A2H
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0 INTB
1
INTB
1
TCLK[4] TOHFP[4] ROH[4] ROHFP[4] TPOS[4] TNEG[4] INTB INTB LCD[4] RSOC
2 1
TOHCLK[4] ROHCLK[4]
1
RPRTY
2
DRCA[4] DTCA[4]
5
INTB
1
INTB INTB
1
1
INTB
1
INTB
1
1. All these register bits must be set to logic 0 for the INTB output to be tristated. If any one of these register bits is a logic 1, then INTB will be driven to logic 0. 2. To enable these outputs, after setting the desired state, RADR[0] must be set to logic 0, RENB must be set to logic 1, bit 4 of register 09BH must be set to logic 1, and RFCLK must transition from logic 0 to logic 1. 3. To enable this output, after setting the desired state, RADR[4:2] must be set equal to PHY_ADR[2:0], RADR[1:0] must be set equal to binary 00, RFCLK must transition from logic 0 to logic 1. 4. To enable this output, after setting the desired state, TADR[4:2] must be set equal to PHY_ADR[2:0], TADR[1:0] must be set equal to binary 00, TFCLK must transition from logic 0 to logic 1. 5. Bit 1 of this register must be logic 0.
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11.2 JTAG Test Port The S/UNI-QJET JTAG Test Access Port (TAP) allows access to the TAP controller and the 4 TAP registers: instruction, bypass, device identification and boundary scan. Using the TAP device input logic levels can be read, device , outputs can be forced, the device can be identified and the device scan path can be bypassed. For more details on the JTAG port, please refer to the Operations section. Table 26 - Instruction Register
Length - 3 bits Instructions EXTEST IDCODE SAMPLE BYPASS BYPASS STCTEST BYPASS BYPASS Selected Register Boundary Scan Identification Boundary Scan Bypass Bypass Boundary Scan Bypass Bypass Instruction Codes, IR[2:0] 000 001 010 011 100 101 110 111
Identification Register Length - 32 bits Version number - 2H Part Number - 7346H Manufacturer's identification code - 0CDH Device identification - 273460CDH
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Table 27
- Boundary Scan Register
Length - 198 bits
Pin/Enable TDAT[15] TDAT[14] TDAT[13] TDAT[12] TDAT[11] TDAT[10] TDAT[9] TDAT[8] TDAT[7] TDAT[6] TDAT[5] TDAT[4] TDAT[3] TDAT[2] TDAT[1] TDAT[0] TFCLK TADR[4] TADR[3] TADR[2] TADR[1] TADR[0] TPRTY TSOC TENB TCA TCA_OEB DTCA[4] DTCA[3] DTCA[2] DTCA[1] PHY_ADR[2] PHY_ADR[1] PHY_ADR[0] ATM8 DRCA[4] DRCA[3] DRCA[2] DRCA[1] RCA
2 1
Register Bit 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39
Cell Type IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL
ID Bit 0 0 1 0 0 1 1 1 0 0 1 1 0 1 0 0 0 1 1 0 0 0 0 0 1 1 0 0 1 1 0 1 (1) (1) (0) (0) (0) (0) (0) (0)
Pin/Enable RX_OEB
4
Register Bit 66 67:70 71:74 75:78 79:82 83:86 87:90 91:94 95:98 99:102 103:106 107:110 111 112;115 116:119 120:123 124:127 128:131 132:135 136:139 140:143 144;147 148:151 152:155 156:159 160:163 164 165 166 167 168 169 170:180 181
Cell Type OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL
ID Bit (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
TICLK[4;1] TIOHM[4:1] TPOH[4:1] TPOHINS[4:1] TPOHCLK[4:1] TPOHFP[4:1] LCD[4:1] RPOH[4:1] RPOHCLK[4:1] REF8KO[4:1] FRMSTAT[4:1] REF8KI ROHCLK[4:1] ROHFP[4:1] ROH[4:1] TOHFP[4:1] TOHCLK[4:1] TOHINS[4:1] TOH[4:1] RCLK[4:1] RNEG[4:1] RPOS[4:1] TCLK[4:1] TNEG[4:1] TPOS[4:1] INTB RSTB WRB RDB ALE CSB A[10:0] D[7] DOENB [7] D[6] DOENB[6] D[5] DOENB [5] D[4]
5 5 5
182 183 184 185 186 187
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RCA_OEB RSOC RENB RFCLK RADR[4] RADR[3] RADR[2] RADR[1] RADR[0] RPRTY
3
40 41 42 43 44 45 46 47 48 49 50:65
OUT_CELL OUT_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL IN_CELL OUT_CELL OUT_CELL
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
DOENB [4] D[3] DOENB [3] D[2] DOENB [2] D[1] DOENB [1] D[0] DOENB [0] HIZ
6
5
188 189 190 191 192 193 194 195 196 197
OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL IO_CELL OUT_CELL OUT_CELL
(0) (0) (0) (0) (0) (0) (0) (0) (0) (0)
5
5
5
5
RDAT[15:0]
NOTES: 1. TDAT[15] is the first bit of the boundary scan chain. 2. TCA_OEB will set TCA to tri-state when set to logic 1. When set to logic 0, TCA will be driven. 3. RCA_OEB will set RCA to tri-state when set to logic 1. When set to logic 0, RCA will be driven. 4. RX_OEB will set RDAT[15:0], RPRTY, and RSOC to tri-state when set to logic 1. When set to logic 0, RDAT[15:0], RPRTY, and RSOC will be driven. 5. The DOENB signals will set the corresponding bidirectional signal (the one preceding the DOENB in the boundary scan chain -- see note 1 also) to an output when set to logic 0. When set to logic 1, the bidirectional signal will be tri-stated. 6. HIZ will set all outputs not controlled by TCA_OEB, RCA_OEB, RX_OEB, and DOENB to tri-state when set to logic 1. When set to logic 0, those outputs will be driven.
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12
OPERATION
12.1 Software Initialization Sequence The S/UNI QJET can come out of reset in a mode that consumes excess power. The device functionality is not altered except for excessive power consumption resulting excess heat dissipation which could lead to long term reliability problems. The software initialization sequence in this section will put the S/UNI QJET into a normal power consumption state should the device come out of reset in the excess power state. This reset sequence must be used to guarantee long term reliability of the device. 1. Reset the S/UNI QJET. 2. Set IOTST (bit 2) in the Master Test Register (datasheet pg. 291) to '1' (by writing 00000100 to register 400H). 3. Put the QJET Receive Cell Processor (RXCP) into test mode by writing: 00000101 to test register 461H 00000101 to test register 561H 00000101 to test register 661H 00000101 to test register 761H 4. Set QJET Receive Cell Processor block built in set test (BIST) controls signals by writing: 01000000 to test register 462H 01000000 to test register 562H 01000000 to test register 662H 01000000 to test register 762H 10101010 to test register 463H 10101010 to test register 563H
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10101010 to test register 663H 10101010 to test register 763H 5. Put the QJET Transmit Cell Processor (TXCP) into test mode by writing: 00000011 to test register 481H 00000011 to test register 581H 00000011 to test register 681H 00000011 to test register 781H 6. Set QJET Transmit Cell Processor block built in set test (BIST) controls signals by writing: 10000000 to test register 480H 10000000 to test register 580H 10000000 to test register 680H 10000000 to test register 780H 10101010 to test register 482H 10101010 to test register 582H 10101010 to test register 682H 10101010 to test register 782H 7. Toggle REF8KI (pin T3, datasheet page 29) signal several times (this provides the clock to the RAM). REF8KI is the test clock used by the TXCP and RXCP blocks when in test mode. 8. Set IOTST (bit 2) in the Master Test register (datasheet pg. 291) to '0' (by writing 00000000 to register 400H). 9. Resume normal device programming.
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12.2 Register Settings for Basic Configurations Table 28 - Register Settings for Basic Configurations
Mode of Operation
S/UNI-QJET Registers (values in Hexadecimal)
x00 T3 C-bit ADM T3 M23 ADM T3 C-bit PLCP T3 M23 PLCP T3 C-bit framer only1 T3 M23 framer only E3 G.832 ADM E3 G.832 framer only1 E3 G.751 ADM E3 G.751 PLCP E3 G.751 framer only J2 ADM J2 framer
1 1
x02 00
x03 00
x04 F8
x08 00
x0C x30 00 83
x34 01
x38 --
x39 --
x40 --
x41 --
x44 --
x4C x60 -04
x61 04
x80 04
x9B 00
C0
C0
00
00
F8
00
00
82
00
--
--
--
--
--
--
04
04
04
00
40
00
00
F8
04
04
83
01
--
--
--
--
--
--
04
00
04
00
40
00
00
F8
04
04
82
00
--
--
--
--
--
--
04
00
04
00
50
00
00
78
00
00
83
01
--
--
--
--
--
--
--
--
--
01
50
00
00
78
00
00
82
00
--
--
--
--
--
--
--
--
--
01
C0
40
40
F8
00
00
--
--
04
00
01
01
--
--
04
08
04
00
50
40
40
78
00
00
--
--
04
00
01
01
--
--
--
--
--
01
C0
40
40
F8
00
00
--
--
00
00
00
01
--
--
04
08
04
00
40
40
40
F8
44
44
--
--
00
04
00
41
--
--
04
00
04
00
50
40
40
78
00
00
--
--
00
00
00
01
--
--
--
--
--
01
C0 50
80 80
80 80
F8 78
00 00
00 00
---
---
---
---
---
---
03 03
0E 0E
04 --
08 --
04 --
00 01
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only1 E1 PLCP E1 ADM T1 PLCP T1 ADM External Framer ADM2 40 40 40 40 40 C0 C0 C0 C0 C0 C0 C0 C0 C0 C0 -----C4 C0 84 80 01 C4 C0 84 80 01 ----------------------------------------04 04 04 04 04 00 00 00 00 00
4
04 04 04 04 04
00 00 00 00 00
1. In framer only modes, TGAPCLK[x] and RGAPCLK[x] are enabled by programming register x01H to 0CH. 2. Byte, nibble, or bit alignment of the ATM Cell bytes to the line overhead is configured using the TOCTA bit in register x00H, and the FORM[1:0] bits in register x0CH. 3. Unipolar mode is selected for DS3, E3, and J2 modes by setting the TUNI bit to logic 1 in register x02H and the UNI bit in x30H, x38H, and x44H respectively. When the DS3, E3, or J2 framers are bypassed, unipolar mode is selected by default. 4. Bit, Nibble, and Byte alignment of the ATM cell octets to the arbitrary external frame overhead is set using the ALIGN[1:0] bits of register x61H. 5. ATM cells are configured to have the Coset Polynomial added to the HCS byte and payload scrambling/descrambling is enabled. 6. ATM Idle cell header octets H1, H2, H3, and H4 are configured to be 00H 00H 00H 01H respectively. 12.3 PLCP Frame Formats The S/UNI-QJET provides support for four different PLCP frame formats: the DS3 PLCP format, the DS1 frame format, the G.751 E3 frame format, and the E1 frame format. The structure of each of these formats is quite similar, and is illustrated in Figure 12 through Figure 15.
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Figure 12
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P11 P10 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
- DS3 PLCP Frame Format
Z6 Z5 Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 POH A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll 5 3 o c te ts T ra ile r 13 or 14 n ib b le s PLCP F ra m e R a te 1 2 5 s
F ra m in g (3 o c te ts )
The DS3 PLCP frame provides the transmission of 12 ATM cells every 125 s. The PLCP frame is nibble aligned to the overhead bits in the DS3 frame; however, there is no relationship between the start of the PLCP frame and the start of the DS3 M-frame. A trailer is inserted at the end of each PLCP frame. The number of nibbles inserted (13 or 14) is varied continuously such that the resulting PLCP frame rate can be locked to an 8 kHz reference.
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Figure 13
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
- DS1 PLCP Frame Format
Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 POH A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll 5 3 o c te ts T ra ile r 6 o c te ts PLCP F ra m e R a te 3 ms
F ra m in g (3 o c te ts )
The DS1 PLCP frame provides the transmission of 10 ATM cells every 3 ms. The PLCP frame is octet aligned to the framing bit in the DS1 frame; there is no relationship between the start of the PLCP frame, and the start of the DS1 frame. A trailer is inserted at the end of each PLCP frame. The number of octets inserted is always six, and cannot be varied. Figure 14
A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 P8 P7 P6 P5 P4 P3 P2 P1 P0
- G.751 E3 PLCP Frame Format
Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 POH A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll 5 3 o c te ts T ra ile r 1 7 ,1 8 ,1 9 ,2 0 , o r 2 1 o c te ts PLCP F ra m e R a te 1 2 5 s
F ra m in g (3 o c te ts )
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The G.751 E3 PLCP frame provides the transmission of 9 ATM cells every 125 s. The PLCP frame is octet aligned to the 16 overhead bits in the ITU-T Recommendation G.751 E3 frame; there is no relationship between the start of the PLCP frame, and the start of the E3 frame. A trailer is inserted at the end of each PLCP frame. The number of octets inserted is nominally 18, 19, or 20, and is based on the number of E3 overhead octets (4, 5, or 6) that have been inserted during the PLCP frame period. The nominal octet stuffing can be varied by 1 octet to allow the E3 PLCP frame to be locked to an external 8 kHz reference. Thus the trailer can be 17, 18, 19, 20, or 21 octets in length. Figure 15
A1 A1 A1 A1 A1 A1 A1 A1 A1 A1 A2 A2 A2 A2 A2 A2 A2 A2 A2 A2 P9 P8 P7 P6 P5 P4 P3 P2 P1 P0
- E1 PLCP Frame Format
Z4 Z3 Z2 Z1 F1 B1 G1 M2 M1 C1 POH A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll A T M C e ll 5 3 o c te ts PLCP F ra m e R a te 2 .3 7 5 m s
F ra m in g (3 o c te ts )
The E1 PLCP frame provides the transmission of 10 ATM cells every 2.375 ms. Thirty of the thirty-two available E1 channels are used for transporting the PLCP frame. The remaining two channels are reserved for E1 framing and signaling functions. The PLCP frame is octet aligned to the channel boundaries in the E1 frame. The PLCP frame is aligned to the 125 s E1 frame (the A1 octet of the first row of the PLCP frame is inserted in timeslot 1 of the E1 frame). 12.3.1 PLCP Path Overhead Octet Processing Table 29 - PLCP Overhead Processing Receive Operation Searches the receive stream for the PLCP frame alignment pattern.
Overhead Field Transmit Operation A1, A2: Inserts the PLCP frame Frame alignment pattern (F628H)
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Overhead Field Alignment Pattern
PO-P11: Path Overhead Identifier Z1-Z6: Growth:
F1: User Channel
B1: Bit Interleaved Parity
Receive Operation When the pattern has been detected for two consecutive rows, along with two valid, and sequential path overhead identifier octets, the S/UNI-QJET declares in-frame. Note that the ATM cell boundaries are implicitly known when the PLCP frame is located, thus cell delineation is accomplished by locating the PLCP frame. When errors are detected in both octets in a single row, or when errors are detected in two consecutive path overhead identifier octets, the S/UNI-QJET declares an out-of-frame defect. The loss-of-frame defect is an integrated version of the out-offrame defect state. Inserts the path overhead Identifies the PLCP path overhead identifier codes in accordance bytes by monitoring the sequence with the PLCP frame of the POI bytes. alignment. See Table 30. These octets are unused and These octets are ignored and are are nominally programmed extracted on the RPOH pin. with all zeros. Access to these octets is provided by the PLCP transmit overhead access port. This octet is unused and the This octet is ignored and is value inserted in this octet is extracted on the RPOH pin. controlled by an internal register or by TPOH pin. This octet contains an 8-bit The bit interleaved parity is interleaved parity (BIP) calculated for the current frame calculated across the entire and stored. The B1 octet PLCP frame (excluding the contained in the subsequent frame A1, A, Pn octets and the is extracted and compared against trailer). The B1 value is the calculated value. Differences calculated based on even between the two values provide an parity and the value inserted indication of the end-to-end bit in the current frame is the BIP error rate. These differences are
Transmit Operation
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Overhead Field
G1: Path Status
M1, M2: Control Information
C1: Cycle/Stuff Counter
Transmit Operation result calculated for the previous frame. The first four bit positions provide a PLCP far end block error function and indicates the number of B1 errors detected at the near end. The FEBE field has nine legal values (0000b-1000b) indicating between zero and eight B1 errors. The fifth bit position is used to transmit PLCP yellow alarm. The last three bit positions provide the link status signal used in IEEE802.6 DQDB implementations. Yellow alarm and link status signal insertion is controlled by the internal registers or by TPOH pin. These octets carry the DQDB layer management information. Internal register controls the nominal value inserted in these octets. These octets are unused in ATM Forum T3 UNI 3.0 specification. The coding of this octet depends on the PLCP frame format. For DS1 and E3 PLCP formats, this octet is programmed with all zeros. For the DS3 PLCP format, this octet indicates the number of stuff nibbles (13 or 14) at the end of each PLCP frame. The C1 value is varied in a three frame cycle where the first frame always
Receive Operation accumulated in a counter in the CPPM block. The G1 byte provides the PLCP FEBE function and is accumulated in an a counter in the CPPM block. PLCP yellow alarm is detected or removed when the yellow bit is set to logic one or zero for ten consecutive frames. The yellow alarm state and the link status signal state are contained in the SPLR Status register.
These octets are ignored and are extracted on the RPOH pin.
Interprets the trailer length according to the selected PLCP frame format and the received C1 code.
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Overhead Field
Transmit Operation contains 13 stuff nibbles, the second frame always contains 14 nibbles, and the third frame contains 13 or 14 nibbles. The stuffing may be varied by a nibble so that the PLCP frame rate can be locked to an external 8 kHz timing reference from REF8KI, a looptimed 8 kHz reference, or fixed stuffing via the FIXSTUFF bit in the SPLT Configuration Register. See Table 31. For the G.751 E3 PLCP format, this octet indicates the number of stuff octets (17 to 21) at the end of the PLCP frame. Depending on the alignment of the G.751 E3 frame to the E3 PLCP frame, 18, 19 or 20 octets are nominally stuffed. The stuffing may be varied by 1 octet so that the PLCP frame rate can be locked to an external 8 kHz timing reference from REF8KI. The S/UNI-QJET also supports fixed timing using the FIXSTUFF bit in the SPLT Configuration Register. See Table 32.
Receive Operation
Table 30
- PLCP Path Overhead Identifier Codes POI P11 P10 POI Code (Hex) 2C 29
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POI P9 P8 P7 P6 P5 P4 P3 P2 P1 P0 Table 31
POI Code (Hex) 25 20 1C 19 15 10 0D 08 04 01
- DS3 PLCP Trailer Length C1(Hex) FF 00 66 99 Frame/Trailer Length 1 (13 Nibbles) 2 (14 Nibbles) 3 (13 Nibbles) 3 (14 Nibbles)
Table 32
- E3 PLCP Trailer Length C1(Hex) 3B 4F 75 9D A7 Trailer Length 17 octets 18 octets 19 octets 20 octets 21 octets
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12.4 DS3 Frame Format The S/UNI-QJET supports both M23 and C-bit parity DS3 framing formats. This format can be extended to support direct byte mapping or PLCP mapping of ATM cells. An overview of the DS3 frame format is shown in Figure 16. Figure 16 - DS3 Frame Structure
6 80 bits (8 blo ck s o f 8 4+1 bits)
M -s ub fra m e 1 2 3 4 5 6 7
X 1 P ayloa d X 2 P ayloa d P 1 P ayloa d P 2 P ayloa d M 1 P ayloa d M 2 P ayloa d M 3 P ayloa d 8 4 b its
F1 F1 F1 F1 F1 F1 F1
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d C 1 P ayloa d
F2 F2 F2 F2 F2 F2 F2
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d C 2 P ayloa d
F3 F3 F3 F3 F3 F3 F3
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d C 3 P ayloa d
F4 F4 F4 F4 F4 F4 F4
P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d P ayloa d
The DS3 receiver decodes a B3ZS-encoded signal and provides indications of line code violations (LCVs). The B3ZS decoding algorithm and the LCV definition are software selectable. While in-frame, the DS3 receiver continuously checks for line code violations, Mbit or F-bit framing bit errors, and P-bit parity errors. When C-bit parity mode is selected, both C-bit parity errors and far end block errors are accumulated. When the C-bit parity framing format is detected, both the far end alarm and control (FEAC) channel and the path maintenance data link are extracted. HDLC messages in the Path Maintenance Data Link are received by an internal data link receiver. The DS3 transmitter allows for the insertion of the overhead bits into a DS3 bit stream and produces a B3ZS-encoded signal. Status signals such as far end receive failure (FERF), the alarm indication signal (AIS) and the idle signal can be inserted when the transmission of these signals is enabled The processing of the overhead bits in the DS3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the TOH[x], TOHINS[x],
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TOHFP[x], and TOHCLK[x] signals. In the receive direction, most of the overhead bits our brought out serially on the ROH[x] data stream. Table 33 Control Bit Xx: X-Bit Channel Px: P-Bit Channel - DS3 Frame Overhead Operation Transmit Operation Inserts the FERF signal on the X-bits. Calculates the parity for the payload data over the previous M-frame and inserts it into the P1 and P2 bit positions. Generates the M-frame alignment signal (M1=0, M2=1, M3=0). Receive Operation Monitors and detects changes in the state of the FERF signal on the X-bits. Calculates the parity for the received payload. Errors are accumulated in internal registers.
Mx: M-Frame Alignment Signal
Fx: M-subframe Alignment Signal
Generates the M-subframe signal (F1=1, F2=0, F3=0, F4=1).
Cx: C-Bit Channels
M23 Operation: The C bits are passed through transparently in M23 framer only mode except for the C-bit Parity ID bit which toggles every M-frame. In M23 ATM applications, the C bits other than the Parity ID bit are forced to logic 1. C-bit Parity Operation: The C-bit Parity ID bit is forced to logic 1. The second C-bit in M-subframe 1 is set to logic 1. The third C-bit in M-subframe 1 provides a far-
Finds the M-frame alignment by searching for the F-bits and the Mbits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. Finds M-frame alignment by searching for the F-bits and the Mbits. Out-of-frame is removed if the M-bits are correct for three consecutive M-frames while no discrepancies have occurred in the F-bits. The state of the C-bit parity ID bit is stored in a register. This bit indicates whether an M23 or C-bit parity format is received. C-bit Parity Operation: The FEAC channel on the third Cbit in M-subframe 1 is detected by the RBOC block. Path parity errors and FEBEs on the C-bits in Msubframes 3 and 4 are accumulated in counters. The path maintenance datalink signal is extracted by the receive HDLC controller.
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Control Bit
Transmit Operation end alarm and control (FEAC) signal. The FEAC channel is sourced by the XBOC block. The 3 C-bits in M-subframe 3 carry path parity information. The value of these 3 C-bits is the same as that of the P-bits. The 3 Cbits in M-subframe 4 are the FEBE bits. The 3 C-bits in Msubframe 5 contain the 28.2 Kbit/s path maintenance datalink. The remaining Cbits are unused and set to logic 1.
Receive Operation
12.5 G.751 E3 Frame Format The S/UNI-QJET provides support for the G.751 E3 frame format. This format can be extended to allow for direct byte mapping or PLCP mapping of ATM cells. The G.751 E3 frame format is shown in Figure 17. Figure 17
1 1 1 1
- G.751 E3 Frame Structure
0 1 0 0 0 0 RAI Na 372 P ayload bits 380 P ayload bits 380 P ayload bits J1 J2 J3 J4 376 P ayload bits
C 11 C 21 C 31 C 41 C 12 C 22 C 32 C 42 C 13 C 23 C 33 C 43
The processing of the overhead bits in the G.751 E3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the TOH[x], TOHINS[x], TOHFP[x], and TOHCLK[x] signals. In the receive direction, most of the overhead bits are brought out serially on the ROH[x] data stream. When used to transport ATM cells in either ATM direct mapping mode or with PLCP framing, bits 13, 14, 15 and 16 of the E3 frame (directly following the RAI and Na bits) are set to 1, 1, 0 and 0.
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Table 34 Control Bit Frame Alignment Signal
- G.751 E3 Frame Overhead Operation Receive Operation Finds frame alignment by searching for the frame alignment signal. When the pattern has been detected for three consecutive frames, an in-frame condition is declared. When errors are detected in four consecutive frames, an out-of-frame condition is declared. Optionally asserts the RAI Extracts the RAI signal and signal under a register control outputs it on the ROH output pin. or when LOS, OOF, AIS and The state of the RAI signal is also LCD conditions are detected. written to a register bit. Asserts the National Use bit Extracts the National Use bit and under a register control or stores the value in a register bit. from the internal HDLC controller. When the device is Extracts the Justification Service configured as an E3 G.751 Bits on the ROH output pin when framer device, the the Cjk bits are configured as Justification Service Bits can overhead. be inserted on the TDATI[x] input pin the same way as normal payload data. When the device is configured for ATM application, the Justification Service Bits are used as payload bits. When the device is Extracts the Tributary Justification configured as a E3 G.751 Bits on the ROH output pin when framer, the Tributary the Jk bits are configured as Justification Bits can be overhead. inserted on the TDATI[x] input pin the same way as normal payload data. When the device is configured for ATM application, the Tributary Justification Bits are used a Transmit Operation Inserts the frame alignment signal 1111010000b.
RAI: Remote Alarm Indication Na: National Use Bit
Cjk: Justification Service Bits
Jk: Tributary Justification Bits
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Control Bit
Transmit Operation payload bits.
Receive Operation
12.6 G.832 E3 Frame Format The S/UNI-QJET provides support for the G.832 E3 frame format. This format can be extended to allow for direct byte mapping of ATM cells. The G.832 E3 frame format is shown in Figure 18. Figure 18 - G.832 E3 Frame Structure
59 colum ns
FA 1 FA 2 EM TR
9 Rows
MA NR GC 530 octet payload
The processing of the overhead bits in the G.832 E3 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data stream using the TOH[x], TOHINS[x], TOHFP[x], and TOHCLK[x] signals. In the receive direction, the overhead bits are brought out serially on the ROH[x] data stream. Table 35 Control FA1, FA2: Frame Alignment Pattern - G.832 E3 Frame Overhead Operation Transmit Operation Inserts the G.832 E3 frame alignment pattern (F628H). Receive Operation Searches the receive stream for the G.832 E3 frame alignment pattern. When the pattern is detected for two consecutive frames, an in-frame condition is declared. Note that there is no ATM cell alignment with the G.832
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Control
EM: Error Monitor, BIP-8
TR: Trail Trace
MA: Maintenance and Adaptation Byte
NR: Network Operator Byte
GC: General Purpose Communication Channel
Receive Operation E3 frame. Therefore cell delineation must be performed to locate the ATM cell boundaries. Inserts the calculated BIP-8 Computes the incoming BIP-8 by computing even parity over value over one 125 s frame. The all transmit bits, including the result is held and compared overhead bits of the previous against the value in the EM byte of 125 s frame. the subsequent frame. Inserts the 16 byte trail Extracts the repetitive trail access access point identifier point identifier and verifies that the specified in internal registers. same pattern is received. Compares the received pattern to the expected pattern programmed in a register. Inserts the FERF, FEBE, Extracts and reports the FERF bit Payload Type bits, Tributary value when it has been the same Unit Multiframe Indicator bits for 3 or 5 consecutive frames. and the Timing Marker bit as S/UNI-QJET also extracts and programmed in a register or accumulates FEBE occurrences as indicated by detection of and extracts the Payload Type, receive OOF or BIP-8 errors. Tributary Unit Multiframe, and Timing Market indicator bits and reports them through microprocessor accessible registers. Inserts the Network Operator Extracts the Network Operator byte byte from the TOH overhead and outputs it on ROH or optionally stream or optionally from the terminates it in the RDLC. All 8 bits TDPR. All 8 bits of the of the Network Operator byte are Network Operator byte are extracted and presented on ROH inserted from TOH or from or to the RDLC. the TDPR. Inserts the GC byte from the Extracts the GC byte and outputs it TOH overhead stream or on ROH or optionally terminates it optionally from the TDPR in the RDLC block. block.
Transmit Operation
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12.7 J2 Frame Format The S/UNI-QJET provides support for the G.704 and NTT J2 frame format. This format can be extended to allow for direct byte mapping of ATM cells as specified in G.804. The J2 frame format consists of 789 bits frames each 125 us long, consisting of 96 bytes of payload, 2 reserved bytes, and 5 F-bits. The frames are grouped into 4 frame multiframes as shown in Figure 19. Figure 19 - J2 Frame Structure
125 uS
Bit # Fram e 1
1-8
9-1 6
17-24
25-32
75 2 760
76 17 68
76 97 76
777 78 4
7 85
78 6
7 87
788
7 89
TS1
TS2 TS2 TS2 TS2
TS3 TS3 TS3 TS3
TS4 TS4 TS4 TS4
T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98 T S 95 T S 96 T S 97 T S 98
1 1 x1 e1
1 0 x2 e2
0 1 x3 e3
0 0 a e4
m 0 m e5
Fram e 2 T S 1 Fram e 3 T S 1 Fram e 4 T S 1
96 O c tets of byte interleaved pa yloa d
The J2 framer decodes a unipolar or B8ZS encoded signal and frames to the resulting 6,312 Kbit/s J2 bit stream. Once in frame, the J2 framer provides indications of frame and multiframe boundaries and marks overhead bits, x-bits, m-bits and reserved channels (TS97 and TS98). Indications of loss of signal, bipolar violations, excessive zeroes, change of frame alignment, framing errors, and CRC errors are provided and accumulated in internal counters. The J2 transmitter inserts the overhead bits into a J2 bit stream and produces a B8ZS-encoded signal. The J2 transmitter adheres to the framing format specified in G.704 and NTT Technical Reference for High Speed Digital Leased Circuit Services. The processing of the overhead bits in the J2 frame is described in the following table. In the transmit direction, the overhead bits can be inserted on a bit-by-bit basis from a user supplied data using the TOH[x], TOHINS[x], TOHFP[x], and TOHCLK[x] signals. In the receive direction, the overhead bits are brought out serially on the ROH[x] data stream.
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Table 36 Control TS1-TS96: Byte Interleaved Payload TS97-TS98: Signaling channels
- J2 Frame Overhead Operation Transmit Operation Receive Operation Inserts the ATM cells into TS1 Extracts the ATM cell octet payload to TS96 octets. and performs cell delineation. Inserts the signaling bytes from either register bits or from the TOH and TOHINS inputs. These bits can be optionally inserted via TDATI input when in framer only mode. Inserts the frame alignment signal automatically. Inserts the 4 KHz data link signal from the internal HDLC controller or from the bit oriented code generator. Inserts the spare bits via register bits or via TOH and TOHINS input pins. Extracts signaling bytes on the ROH output.
Frame Alignment Signal M-bits: 4kHz Data Link
Finds J2 frame alignment by searching for the frame alignment signal. Extracts the 4 KHz data link signal for the internal HDLC controller.
X-bits: Spare Bits
A-bit: Remote Loss of Frame Indication
Inserts the A-bit via register bit. The A-bit can be optionally be asserted when the J2 framer is in loss of frame condition. Automatically calculates and inserts the CRC-5 check sequence.
E1-E5: CRC-5 Check Sequence
Extracts and presents the x-bits on register bits. The X-bit states can be debounced and presented on the ROH output pin. An interrupt change can be generated to signal a change in the X-bit state. Extracts and presents the A-bit on a register bit. The A-bit state can be debounced and presented on the ROH output pin. An interrupt can be generated to signal a change in the A-bit state. Calculates the CRC-5 check sequence for the received data stream. Discrepancies with the received CRC-5 code can be configured to generate an interrupt. CRC-5 errors are accumulated in an internal counter.
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12.8 S/UNI-QJET Cell Data Structure ATM cells may be passed to/from the S/UNI-QJET using a 26 word data structure, a 27 word data structure, a 52 word, or a 53 word data structure. These data structures are shown in Figure 20, Figure 21, Figure 22, and Figure 23. Figure 20 - 16-bit Wide, 26 Word Structure
B it 15 W ord 1 W ord 2 W ord 3 W ord 4 W ord 5
H1 H3 P A YL O A D 1 P A YL O A D 3 P A YL O A D 5
B it 8
B it 7
H2 H4 P A YL O A D 2 P A YL O A D 4 P A YL O A D 6
B it 0
W ord 26
P A YL O A D 4 7
P A YL O A D 4 8
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Figure 21
- 16-bit Wide, 27 Word Structure
B it 15 B it 8
H1 H3 H5 P A YL O A D 1 P A YL O A D 3 P A YL O A D 5
B it 7
H2 H4
B it 0
W ord 1 W ord 2 W ord 3 W ord 4 W ord 5 W ord 6
HC S S T A T U S /C O N T R O L
P A YL O A D 2 P A YL O A D 4 P A YL O A D 6
W ord 27
P A YL O A D 4 7
P A YL O A D 4 8
The 16-bit SCI-PHY compliant data structure is selected when the ATM8 input is tied low. Bit 15 of each word is the most significant bit (which corresponds to the first bit transmitted or received). Selection between the 26 word and 27 word structure is done with the DS27_53 register bit in the S/UNI-QJET Configuration 1 register. The 26 word structure is chosen when DS27_53 is set to logic 0. The 27 word structure is chosen when DS27_53 is set to logic 1. The start of cell indication input and output (TSOC and RSOC) are coincident with Word 1 (containing the first two header octets). The header check sequence octet (HCS) is only passed through the 27 word structure. Word 3 of this structure contains the HCS octet in bits 15 to 8. In the receive direction with the 27 word structure, the lower 8 bits of Word 3 contain the HCS status octet. An all-zeros pattern in these 8 bits indicates that the associated header is error free. An all-ones pattern indicates that the header contains an uncorrectable error (if the HCSPASS bit in the RXCP-50 Configuration 2 Register is set to logic zero, the all-ones pattern will never be passed in this structure). An alternating ones and zeros pattern (xxAA) indicates that the header contained a correctable error. In this case the header passed through the structure is the "corrected" header.
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In the transmit direction, with the 27 word structure, the HCSB bit in the TXCP-50 Configuration 1 register determines whether the HCS is calculated internally or is inserted directly from the upper 8 bits of Word 3. The lower 8 bits of Word 3 contain the HCS control octet. The HCS control octet is an error mask that allows the insertion of one or more errors in the HCS octet. A logic one in a given bit position causes the inversion of the corresponding HCS bit position (for example a logic one in bit 7 causes the most significant bit of the HCS to be inverted). With the 26 word structure, if the HCSB bit in the TXCP-50 is logic 1, then no HCS byte is inserted on the data read from the Utopia interface or on the Idle cells. In such a configuration, the RXCP-50 should be configured to pass the 26 word output without requiring cell delineation by setting the CCDIS bit to logic 1. This setting is useful for passing arbitrary payload through the transmit and receive Utopia interfaces. Figure 22 - 8-bit Wide, 52 Word Structure
B it 7 W ord 1 W ord 2 W ord 3 W ord 4 W ord 5
H1 H2 H3 H4 P A YL O A D 1
B it 0
W ord 52
P A YL O A D 4 8
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Figure 23
- 8-bit Wide, 53 Word Structure
B it 7 W ord 1 W ord 2 W ord 3 W ord 4 W ord 5 W ord 6
H1 H2 H3 H4 H5 PAYLO AD1
B it 0
W ord 53
P A YL O A D 4 8
The 8-bit SCI-PHY compliant data structure is selected when the ATM8 input is tied high. Bit 7 of each word is the most significant bit (which corresponds to the first bit transmitted or received). Selection between the 52-byte and 53-byte structures is done by the DS27_53 register bit in the S/UNI-QJET Configuration 1 register. The 52 byte structure is chosen when DS27_53 is set to logic 0. The 53 byte structure is chosen when DS27_53 is set to logic 1. The start of cell indication input and output (TSOC and RSOC) are coincident with Word 1 (containing the first cell header octet). The header check sequence octet (HCS) is passed through the 53 byte structure. Word 5 of this structure contains the HCS octet. In the receive direction, cells containing "detected and uncorrected" header errors are dropped when the HCSPASS bit in the RXCP-50 Configuration 2 Register is set to logic zero. No HCS status information is passed within this data structure. Cells with error free headers and "detected and corrected" headers are passed when HCSPASS and DISCOR are logic zero. Cells containing uncorrectable HCS errors are dropped while the HCSPASS bit is set to logic zero. Error free headers, "detected and corrected" headers, and "detected and uncorrected" headers are passed when HCSPASS is a logic one.
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In the receive direction, idle cells are dropped when the IDLEPASS bit in the RXCP-50 Configuration 2 Register is set to a logic 0. No cells are passed when the S/UNI-QJET is in the PLCP loss of frame defect state (for PLCP based transmission), or when the S/UNI-QJET is in the out of cell delineation defect state (for non-PLCP based transmission). In the transmit direction, the HCSB bit in the TXCP-50 Configuration 1 Register determines whether the HCS is calculated internally or is inserted directly from Word 5. For the 52 byte structure, if the HCSB bit in the TXCP-50 is logic 1, then no HCS byte is inserted and the TXCP-50 will only transmit the data present on the 52 words. In such a configuration, the RXCP-50 should be configured to pass the 52 word output without requiring cell delineation by setting the CCDIS bit to logic 1. This setting is useful for passing arbitrary payload through the transmit and receive Utopia interfaces. 12.9 Resetting the RXFF and TXFF FIFOs Resetting the receive and transmit FIFOs can be accomplished using the FIFORST bits (RXCP-50 FIFO/UTOPIA Control & Config, TXCP-50 Configuration 1 registers). When resetting, the FIFORST bit should be written with a logic 1, and held for two or more clock cycles (the longer of two Utopia clock cycles or 16 line clock cycles). After de-asserting FIFORST, data can be safely written to the TXFF after two or more clock cycles have passed. 12.10 Servicing Interrupts The S/UNI-QJET will assert INTB to logic 0 when a condition which is configured to produce an interrupt occurs. To find which condition caused this interrupt to occur, the procedure outlined below should be followed: 1. Read the INT[4:1] bits of the S/UNI-QJET Clock Activity Monitor and Interrupt Identification register (007H) to identify which quadrant of the S/UNI-QJET produced the interrupt. For example, a logic one on the INT[3] register bit indicates that quadrant number 3 of the S/UNI-QJET produced the interrupt. 2. Having identified the quadrant which produced the interrupt, read the S/UNI-QJET Interrupt Status Register (005H, 105H, 205H, and 305H) to identify which block in the quadrant produced the interrupt. For example, a logic one on the TDPRI register bit in register 205H indicates that the TDPR block in quadrant number 3 of the S/UNI-QJET produced the interrupt. 3. Service the interrupt.
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4. If the INTB pin is still logic 0, then there are still interrupts to be serviced. Otherwise, all interrupts have been serviced. Wait for the next assertion of INTB. 12.11 Using the Performance Monitoring Features The PMON and CPPM blocks are provided for performance monitoring purposes. The RXCP-50 and TXCP-50 also contain performance monitor registers. The PMON block is used to monitor DS3, E3, and J2 performance primitives while the CPPM is used to monitor PLCP and idle-cell-based primitives. The RXCP-50 is used to monitor received cell primitives, and the TXCP-50 is used to monitor transmit cell primitives. The counters in the PMON block have been sized as not to saturate if polled every second. The counters in the CPPM blocks have been sized as not to saturate if polled every 1/2 second at line rates up to 44.736 MHz. The counters in the RXCP-50 and TXCP-50 have been sized to not saturate if polled every second at line rates up to 44.736 MHz. The DS3, E3, and J2 primitives can be accumulated independently of the PLCP and cell-based primitives. An accumulation interval is initiated by writing to one of the PMON event counter register addresses. After writing to a PMON count register, a number of RCLK clock periods (3 for J2 mode, 255 for DS3 mode, 500 for G.832 E3 mode, and 3 for G.751 E3 mode) must be allowed to elapse to permit the PMON counter values to be properly transferred. The PMON registers may then be read. PLCP and cell-based primitives can be accumulated independent of the DS3, E3, or J2 primitives. An accumulation interval is initiated by writing to one of the CPPM event counter register addresses. After writing to a CPPM count register, a maximum of 67 RCLK clock periods must be allowed to elapse to permit all the CPPM values to be properly transferred. The CPPM registers may then be read. The RXCP-50 and TXCP-50 accumulate cell-based primitives such as received cells, corrected cell headers, uncorrected cell headers, and transmitted cells. An accumulation interval in each block is initiated by writing to one of the RXCP-50 or TXCP-50 event counter register addresses. After writing to a count register, a maximum of 67 RCLK or TICLK clock periods must be allowed to elapse to permit all the RXCP-50 or TXCP-50 values to be properly transferred. The RXCP-50 or TXCP-50 count registers may then be read. Writing to the S/UNI-QJET Identification, Master Reset, and Global Monitor Update register causes the PMON, CPPM, RXCP-50, and TXCP-50 performance event counters to latch and a new accumulation period to start in all four quadrants of the S/UNI-QJET. A maximum of 67 RCLK[x] clock periods
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must be allowed to elapse to permit all the event count registers to be properly transferred. 12.12 Using the Internal FDL Transmitter It is important to note that the access rate to the TDPR registers is limited by the rate of the internal high-speed system clock selected by the LINESYSCLK register bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). Consecutive accesses to the TDPR Configuration, TDPR Interrupt Status/UDR Clear, and TDPR Transmit Data register should be accessed (with respect to WRB rising edge and RDB falling edge) at a rate no faster than 1/8 that of the selected TDPR high-speed system clock. This time is used by the high-speed system clock to sample the event, write the FIFO, and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the line clock) must be considered when determining the procedure used to read and write the TDPR registers. Upon reset of the S/UNI-QJET, the TDPR should be disabled by setting the EN bit in the TDPR Configuration Register to logic 0 (default value). An HDLC allones Idle signal will be sent while in this state. The TDPR is enabled by setting the EN bit to logic 1. The FIFOCLR bit should be set and then cleared to initialize the TDPR FIFO. The TDPR is now ready to transmit. To initialize the TDPR, the TDPR Configuration Register must be properly set. If FCS generation is desired, the CRC bit should be set to logic 1. If the block is to be used in interrupt driven mode, then interrupts should be enabled by setting the FULLE, OVRE, UDRE, and LFILLE bits in the TDPR Interrupt Enable register to logic 1. The TDPR operating parameters in the TDPR Upper Transmit Threshold and TDPR Lower Interrupt Threshold registers should be set to the desired values. The TDPR Upper Transmit Threshold sets the value at which the TDPR automatically begins the transmission of HDLC packets, even if no complete packets are in the FIFO. Transmission will continue until current packet is transmitted and the number of bytes in the TDPR FIFO falls to, or below, this threshold level. The TDPR will always transmit all complete HDLC packets (packets with EOM attached) in its FIFO. Finally, the TDPR can be enabled by setting the EN bit to logic 1. If no message is sent after the EN bit is set to logic 1, continuous flags will be sent. The TDPR can be used in a polled or interrupt driven mode for the transfer of data. In the polled mode the processor controlling the TDPR must periodically read the TDPR Interrupt Status register to determine when to write to the TDPR Transmit Data register. In the interrupt driven mode, the processor controlling the TDPR uses the INTB output, the S/UNI-QJET Clock Activity Monitor and
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Interrupt Identification register, and the S/UNI-QJET Interrupt Status register to identify TDPR interrupts which determine when writes can or must be done to the TDPR Transmit Data register. Interrupt Driven Mode The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 1 so an interrupt on INTB is generated upon detection of a FIFO full state, a FIFO depth below the lower limit threshold, a FIFO overrun, or a FIFO underrun. The following procedure should be followed to transmit HDLC packets: 1. Wait for data to be transmitted. Once data is available to be transmitted, then go to step 2. 2. Write the data byte to the TDPR Transmit Data register. 3. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 4. If there are more bytes in the packet to be sent, then go to step 2. While performing steps 1 to 4, the processor should monitor for interrupts generated by the TDPR. When an interrupt is detected, the TDPR Interrupt Routine detailed in the following text should be followed immediately. The TDPR will force transmission of the packet information when the FIFO depth exceeds the threshold programmed with the UTHR[6:0] bits in the TDPR Upper Transmit Threshold register. Unless an error condition occurs, transmission will not stop until the last byte of all complete packets is transmitted and the FIFO depth is at or below the threshold limit. The user should watch the FULLI and LFILLI interrupts to prevent overruns and underruns. TDPR Interrupt Routine Upon assertion of INTB, the source of the interrupt must first be identified by reading the S/UNI-QJET Clock Activity Monitor and Interrupt Identification register (007H) and the S/UNI-QJET Interrupt Status registers (005H, 105H,
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205H, 305H). Once the source of the interrupt has been identified as TDPR, then the following procedure should be carried out: 1. Read the TDPR Interrupt Status register. 2. If UDRI=1, then the FIFO has underrun and the last packet transmitted has been corrupted and needs to be retransmitted. When the UDRI bit transitions to logic 1, one Abort sequence and continuous flags will be transmitted. The TDPR FIFO is held in reset state. To reenable the TDPR FIFO and to clear the underrun, the TDPR Interrupt Status/UDR Clear register should be written with any value. 3. If OVRI=1, then the FIFO has overflowed. The packet which the last byte written into the FIFO belongs to has been corrupted and must be retransmitted. Other packets in the FIFO are not affected. Either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If the FIFO overflows on the packet currently being transmitted (packet is greater than 128 bytes long), OVRI is set, an Abort signal is scheduled to be transmitted, the FIFO is emptied, and then flags are continuously sent until there is data to be transmitted. The FIFO is held in reset until a write to the TDPR Transmit Data register occurs. This write contains the first byte of the next packet to be transmitted. 4. If FULLI=1 and FULL=1, then the TDPR FIFO is full and no further bytes can be written. When in this state, either a timer can be used to determine when sufficient bytes are available in the FIFO or the user can wait until the LFILLI interrupt is set, indicating that the FIFO depth is at the lower threshold limit. If FULLI=1 and FULL=0, then the TDPR FIFO had reached the FULL state earlier, but has since emptied out some of its data bytes and now has space available in its FIFO for more data. 5. If LFILLI=1 and BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. If there is more data to transmit, then it should be written to the TDPR Transmit Data register before an underrun occurs. If there is no more data to transmit, then an EOM should be set at the end of the last packet byte. Flags will then be transmitted once the last packet has been transmitted.
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If LFILLI=1 and BLFILL=0, then the TDPR FIFO had fallen below the lowerthreshold state earlier, but has since been refilled to a level above the lowerthreshold level. Polling Mode The TDPR automatically transmits a packet once it is completely written into the TDPR FIFO. The TDPR also begins transmission of bytes once the FIFO level exceeds the programmable Upper Transmit Threshold. The CRC bit can be set to logic 1 so that the FCS is generated and inserted at the end of a packet. The TDPR Lower Interrupt Threshold should be set to such a value that sufficient warning of an underrun is given. The FULLE, LFILLE, OVRE, and UDRE bits are all set to logic 0 since packet transmission is set to work with a periodic polling procedure. The following procedure should be followed to transmit HDLC packets: 1. Wait until data is available to be transmitted, then go to step 2. 2. Read the TDPR Interrupt Status register. 3. If FULL=1, then the TDPR FIFO is full and no further bytes can be written. Continue polling the TDPR Interrupt Status register until either FULL=0 or BLFILL=1. Then, go to either step 4 or 5 depending on implementation preference. 4. If BLFILL=1, then the TDPR FIFO depth is below its lower threshold limit. Write the data into the TDPR Transmit Data register. Go to step 6. 5. If FULL=0, then the TDPR FIFO has room for at least 1 more byte to be written. Write the data into the TDPR Transmit Data register. Go to step 6. 6. If more data bytes are to be transmitted in the packet, then go to step 2. 7. If all bytes in the packet have been sent, then set the EOM bit in the TDPR Configuration register to logic 1. Go to step 1. 12.13 Using the Internal Data Link Receiver It is important to note that the access rate to the RDLC registers is limited by the rate of the internal high-speed system clock selected by the LINESYSCLK register bit of the S/UNI-QJET Misc. register (09BH, 19BH, 29BH, 39BH). Consecutive accesses to the RDLC Status and RDLC Data registers should be accessed at a rate no faster than 1/10 that of the selected RDLC high-speed system clock. This time is used by the high-speed system clock to sample the
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event and update the FIFO status. Instantaneous variations in the high-speed reference clock frequencies (e.g. jitter in the receive line clock) must be considered when determining the procedure used to read RDLC registers. On power up of the system, the RDLC should be disabled by setting the EN bit in the Configuration Register to logic 0 (default state). The RDLC Interrupt Control register should then be initialized to enable the INT output and to select the FIFO buffer fill level at which an interrupt will be generated. If the INTE bit is not set to logic 1, the RDLC Status register must be continuously polled to check the interrupt status (INTR) bit. After the RDLC Interrupt Control register has been written, the RDLC can be enabled at any time by setting the EN bit in the RDLC Configuration register to logic 1. When the RDLC is enabled, it will assume the link status is idle (all ones) and immediately begin searching for flags. When the first flag is found, an interrupt will be generated, and a dummy byte will be written into the FIFO buffer. This is done to provide alignment of link up status with the data read from the FIFO. When an abort character is received, another dummy byte and link down status is written into the FIFO. This is done to provide alignment of link down status with the data read from the FIFO. It is up to the controlling processor to check the COLS bit in the RDLC Status register for a change in the link status. If the COLS bit is set to logic 1, the FIFO must be emptied to determine the current link status. The first flag and abort status encoded in the PBS bits is used to set and clear a Link Active software flag. When the last byte of a properly terminated packet is received, an interrupt is generated. While the RDLC Status register is being read the PKIN bit will be logic 1. This can be a signal to the external processor to empty the bytes remaining in the FIFO or to just increment a number-of-packets-received count and wait for the FIFO to fill to a programmable level. Once the RDLC Status register is read, the PKIN bit is cleared to logic 0 . If the RDLC Status register is read immediately after the last packet byte is read from the FIFO, the PBS[2] bit will be logic 1 and the CRC and non-integer byte status can be checked by reading the PBS[1:0] bits. When the FIFO fill level is exceeded, an interrupt is generated. The FIFO must be emptied to remove this source of interrupt. The RDLC can be used in a polled or interrupt driven mode for the transfer of frame data. In the polled mode, the processor controlling the RDLC must periodically read the RDLC Status register to determine when to read the RDLC Data register. In the interrupt driven mode, the processor controlling the RDLC uses the S/UNI-QJET INTB output, the S/UNI-QJET Clock Activity Monitor and
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Interrupt Identification register, and the S/UNI-QJET Interrupt Status registers to determine when to read the RDLC Data register. In the case of interrupt driven data transfer from the RDLC to the processor, the INTB output of the S/UNI-QJET is connected to the interrupt input of the processor. The processor interrupt service routine verifies what block generated the interrupt by reading the S/UNI-QJET Clock Activity Monitor and Interrupt Identification register, and the S/UNI-QJET Interrupt Status registers. Once it has identified that the RDLC has generated the interrupt, it processes the data in the following order: 1. RDLC Status register read. The INTR bit should be logic 1. 2. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 3. If COLS = 1, then set the EMPTY FIFO software flag. 4. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 5. Read the RDLC Data register. 6. Read the RDLC Status register. 7. If OVR = 1, then discard last frame and go to step 1. Overrun causes a reset of FIFO pointers. Any packets that may have been in the FIFO are lost. 8. If COLS = 1, then set the EMPTY FIFO software flag. 9. If PKIN = 1, increment the PACKET COUNT. If the FIFO is desired to be emptied as soon as a complete packet is received, set the EMPTY FIFO software flag. If the EMPTY FIFO software flag is not set, FIFO emptying will delayed until the FIFO fill level is exceeded. 10. Start the processing of FIFO data. Use the PBS[2:0] packet byte status bits to decide what is to be done with the FIFO data. 10.1) If PBS[2:0] = 001, discard data byte read in step 5 and set the LINK ACTIVE software flag. 10.2) If PBS[2:0] = 010, discard the data byte read in step 5 and clear the LINK ACTIVE software flag.
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10.3) If PBS[2:0] = 1XX, store the last byte of the packet, decrement the PACKET COUNT, and check the PBS[1:0] bits for CRC or NVB errors before deciding whether or not to keep the packet. 10.4) If PBS[2:0] = 000, store the packet data.
11. If FE = 0 and INTR = 1 or FE = 0 and EMPTY FIFO = 1, go to step 5 else clear the EMPTY FIFO software flag and leave this interrupt service routine to wait for the next interrupt. The link state is typically a local software variable. The link state is inactive if the RDLC is receiving all ones or receiving bit-oriented codes which contain a sequence of eight ones. The link state is active if the RDLC is receiving flags or data. If the RDLC data transfer is operating in the polled mode, processor operation is exactly as shown above for the interrupt driven mode, except that the entry to the service routine is from a timer, rather than an interrupt. Figure 24
B IT : 8
0
- Typical Data Frame
7
1
6
1
5
1
4
1
3
1
2
1
1
0
FLA G
Address (high) (lo w) data byte s written to the T ransm it D ata R egister and s erially transm itted, bit 1 first
CONTROL
Fram e C hec k Seq uenc e 0 1 1 1 1 1 1 0
appended after E O M is set, if CR C is set
FLA G
Bit 1 is the first serial bit to be received. When enabled, the primary, secondary and universal addresses are compared with the high order packet address to determine a match.
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Figure 25
- Example Multi-Packet Operational Sequence
DATA INT FE LA
FF F D D D D F D D D D D D D D DD A FF F F DD D D FF 1 2 3 45 6 7
F A D INT FE LA
- flag sequence (01111110) - abort sequence (01111111) - packet data bytes - active high interrupt output - internal FIFO empty status - state of the LINK ACTIVE software flag
Figure 25 shows the timing of interrupts, the state of the FIFO, and the state of the Data Link relative the input data sequence. The cause of each interrupt and the processing required at each point is described in the following paragraphs. At points 1 and 5 the first flag after all ones or abort is detected. A dummy byte is written in the FIFO, FE goes low, and an interrupt goes high. When the interrupt is detected by the processor it reads the dummy byte, the FIFO becomes empty, and the interrupt is removed. The LINK ACTIVE (LA) software flag is set to logic 1. At points 2 and 6 the last byte of a packet is detected and interrupt goes high. When the interrupt is detected by the processor, it reads the data and status registers until the FIFO becomes empty. The interrupt is removed as soon as the RDLC Status register is read since the FIFO fill level of 8 bytes has not been exceeded. It is possible to store many packets in the FIFO and empty the FIFO when the FIFO fill level is exceeded. In either case the processor should use this interrupt to count the number of packets written into the FIFO. The packet count or a software time-out can be used as a signal to empty the FIFO.
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At point 3 the FIFO fill level of 8 bytes is exceeded and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. At points 4 or 7 an abort character is detected, a dummy byte is written into the FIFO, and interrupt goes high. When the interrupt is detected by the processor it must read the data and status registers until the FIFO becomes empty and the interrupt is removed. The LINK ACTIVE software flag is cleared. 12.14 PRGD Pattern Generation A pseudo-random or repetitive pattern can be inserted/extracted in the PLCP payload (if PLCP framing is enabled) or in the DS3, E3, J2, or Arbitrary framing format payload (if PLCP framing is disabled). It cannot be inserted into the ATM cell payload. The pattern generator can be configured to generate pseudo random patterns or repetitive patterns as shown in Figure 26 below: Figure 26 - PRGD Pattern Generator
LENGTH PS TAP
1
2
3
32
The pattern generator consists of a 32 bit shift register and a single XOR gate. The XOR gate output is fed into the first stage of the shift register. The XOR gate inputs are determined by values written to the length register (PL[4:0]) and the tap register (PT[4:0], when the PS bit is low). When PS is high, the pattern detector functions as a recirculating shift register, with length determined by PL[4:0]. 12.14.1 Generating and detecting repetitive patterns
When a repetitive pattern (such as 1-in-8) is to be generated or detected, the PS bit must be set to logic 1. The pattern length register must be set to (N-1), where N is the length of the desired repetitive pattern. Several examples of
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programming for common repetitive sequences are given below in the Common Test Patterns section. For pattern generation, the desired pattern must be written into the PRGD Pattern Insertion registers. The repetitive pattern will then be continuously generated. The generated pattern will be inserted in the output data stream, but the phase of the pattern cannot be guaranteed. For pattern detection, the PRGD will determine if a repetitive pattern of the length specified in the pattern length register exists in the input stream. It does so by loading the first N bits from the data stream, and then monitoring to see if the pattern loaded repeats itself error free for the subsequent 48 bit periods. It will repeat this process until it finds a repetitive pattern of length N, at which point it begins counting errors (and possibly re-synchronizing) in the same way as for pseudo-random sequences. Note that the PRGD does NOT look for the pattern loaded into the Pattern Insertion registers, but rather automatically detects any repetitive pattern of the specified length. The precise pattern detected can be determined by initiating a PRGD update, setting PDR[1:0] = 00 in the PRGD Control register, and reading the Pattern Detector registers (which will then contain the 32 bits detected immediately prior to the strobe). 12.14.2 Common Test Patterns
The PRGD can be configured to monitor the standardized pseudo random and repetitive patterns described in ITU-T O.151. The register configurations required to generate these patterns and others are indicated in the two tables below: Table 37 - Pseudo Random Pattern Generation (PS bit = 0) TR 00 00 01 04 00 03 LR 02 03 04 05 06 06 IR#1 FF FF FF FF FF FF IR#2 FF FF FF FF FF FF IR#3 FF FF FF FF FF FF IR#4 FF FF FF FF FF FF TINV 0 0 0 0 0 0 RINV 0 0 0 0 0 0
Pattern Type 23 -1 24 -1 25-1 26 -1 27 -1 27 -1 (Fractional T1 LB Activate)
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27 -1 (Fractional T1 LB Deactivate) 29 -1 (O.153) 210 -1 211 -1 (O.152, O.153) 215 -1 (O.151) 217 -1 218 -1 220 -1 (O.153) 220 -1 (O.151 QRSS bit=1) 221 -1 222 -1 223 -1 (O.151) 225 -1 228 -1 229 -1 231 -1 Table 38
03 04 02 08 0D 02 06 02 10
06 08 09 0A 0E 10 11 13 13
FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF
FF FF FF FF FF FF FF FF FF
1 0 0 0 1 0 0 0 0
1 0 0 0 1 0 0 0 0
01 00 11 02 02 01 02
14 15 16 18 1B 1C 1E
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
FF FF FF FF FF FF FF
0 0 1 0 0 0 0
0 0 1 0 0 0 0
- Repetitive Pattern Generation (PS bit = 1) TR 00 00 00 00 00 LR 00 00 01 03 17 IR#1 FF FE FE FC 22 IR#2 FF FF FF FF 00 IR#3 FF FF FF FF 20 IR#4 FF FF FF FF FF TINV 0 0 0 0 0 RINV 0 0 0 0 0
Pattern Type All ones All zeros Alternating ones/zeros Double alternating ones/zeros 3 in 24
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1 in 16 1 in 8 1 in 4 Inband loopback activate Inband loopback deactivate
00 00 00 00 00
0F 07 03 04 02
01 01 F1 F0 FC
00 FF FF FF FF
FF FF FF FF FF
FF FF FF FF FF
0 0 0 0 0
0 0 0 0 0
Notes for the Pseudo Random and Repetitive Pattern Generation Tables 1. The PS bit and the QRSS bit are contained in the TDPR Control register 2. TR = TDPR Tap Register 3. LR = TDPR Length Register 4. IR#1 = TDPR Pattern Insertion #1 Register 5. IR#2 = TDPR Pattern Insertion #2 Register 6. IR#3 = TDPR Pattern Insertion #3 Register 7. IR#4 = TDPR Pattern Insertion #4 Register 8. The TINV bit and the RINV bit are contained in the TDPR Control register 12.15 JTAG Support The S/UNI-QJET supports the IEEE Boundary Scan Specification as described in the IEEE 1149.1 standards. The Test Access Port (TAP) consists of the five standard pins, TRSTB, TCK, TMS, TDI and TDO used to control the TAP controller and the boundary scan registers. The TRSTB input is the active-low reset signal used to reset the TAP controller. TCK is the test clock used to sample data on input, TDI and to output data on output, TDO. The TMS input is used to direct the TAP controller through its states. The basic boundary scan architecture is shown below.
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Figure 27
- Boundary Scan Architecture
TDI
Boundary S can R egister
D ev ic e Identification R egister
Bypass R egister
Instruction R egister and D ec ode
M ux D FF
TDO
TMS T est A ccess P o rt C ontroller TRSTB TCK
C ontrol S e lect T ri-state E nable
The boundary scan architecture consists of a TAP controller, an instruction register with instruction decode, a bypass register, a device identification register and a boundary scan register. The TAP controller interprets the TMS input and generates control signals to load the instruction and data registers. The instruction register with instruction decode block is used to select the test to be executed and/or the register to be accessed. The bypass register offers a singlebit delay from primary input, TDI to primary output, TDO. The device identification register contains the device identification code. The boundary scan register allows testing of board inter-connectivity. The boundary scan register consists of a shift register place in series with device inputs and outputs. Using the boundary scan register, all digital inputs can be
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sampled and shifted out on primary output, TDO. In addition, patterns can be shifted in on primary input, TDI and forced onto all digital outputs. TAP Controller The TAP controller is a synchronous finite state machine clocked by the rising edge of primary input, TCK. All state transitions are controlled using primary input, TMS. The finite state machine is described below.
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Figure 28
- TAP Controller Finite State Machine
T R S T B =0 T est-LogicR eset 1 0 R un-T estIdle 0 1 1 S elect-D R S can 0 C aptureDR 0 S hiftDR 1 E xit1DR 0 P auseDR 1 0 E xit2DR 1 U pdateDR 1 0 0 0 0 1 1 1 S elect-IR S can 0 C aptureIR 0 S hiftIR 1 E xit1IR 0 P auseIR 1 E xit2IR 1 U pdateIR 1 0 0 0 1 1
A ll transitions dependent on input T M S
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Test-Logic-Reset The test logic reset state is used to disable the TAP logic when the device is in normal mode operation. The state is entered asynchronously by asserting input, TRSTB. The state is entered synchronously regardless of the current TAP controller state by forcing input, TMS high for 5 TCK clock cycles. While in this state, the instruction register is set to the IDCODE instruction. Run-Test-Idle The run test/idle state is used to execute tests. Capture-DR The capture data register state is used to load parallel data into the test data registers selected by the current instruction. If the selected register does not allow parallel loads or no loading is required by the current instruction, the test register maintains its value. Loading occurs on the rising edge of TCK. Shift-DR The shift data register state is used to shift the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK. Update-DR The update data register state is used to load a test register's parallel output latch. In general, the output latches are used to control the device. For example, for the EXTEST instruction, the boundary scan test register's parallel output latches are used to control the device's outputs. The parallel output latches are updated on the falling edge of TCK. Capture-IR The capture instruction register state is used to load the instruction register with a fixed instruction. The load occurs on the rising edge of TCK. Shift-IR The shift instruction register state is used to shift both the instruction register and the selected test data registers by one stage. Shifting is from MSB to LSB and occurs on the rising edge of TCK.
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Update-IR The update instruction register state is used to load a new instruction into the instruction register. The new instruction must be scanned in using the Shift-IR state. The load occurs on the falling edge of TCK. The Pause-DR and Pause-IR states are provided to allow shifting through the test data and/or instruction registers to be momentarily paused. Boundary Scan Instructions The following is an description of the standard instructions. Each instruction selects an serial test data register path between input, TDI and output, TDO. BYPASS The bypass instruction shifts data from input, TDI to output, TDO with one TCK clock period delay. The instruction is used to bypass the device. EXTEST The external test instruction allows testing of the interconnection to other devices. When the current instruction is the EXTEST instruction, the boundary scan register is place between input, TDI and output, TDO. Primary device inputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state. Primary device outputs can be controlled by loading patterns shifted in through input TDI into the boundary scan register using the Update-DR state. SAMPLE The sample instruction samples all the device inputs and outputs. For this instruction, the boundary scan register is placed between TDI and TDO. Primary device inputs and outputs can be sampled by loading the boundary scan register using the Capture-DR state. The sampled values can then be viewed by shifting the boundary scan register using the Shift-DR state.
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IDCODE The identification instruction is used to connect the identification register between TDI and TDO. The device's identification code can then be shifted out using the Shift-DR state. STCTEST The single transport chain instruction is used to test out the TAP controller and the boundary scan register during production test. When this instruction is the current instruction, the boundary scan register is connected between TDI and TDO. During the Capture-DR state, the device identification code is loaded into the boundary scan register. The code can then be shifted out output, TDO using the Shift-DR state. Boundary Scan Cell Description In the following diagrams, CLOCK-DR is equal to TCK when the current controller state is SHIFT-DR or CAPTURE-DR, and unchanging otherwise. The multiplexer in the center of the diagram selects one of four inputs, depending on the status of select lines G1 and G2. The ID Code bit is as listed in the Boundary Scan Register table located in the TEST FEATURES DESCRIPTION - JTAG Test Port section. Figure 29
IDC O D E Sc an C hain O ut
- Input Observation Cell (IN_CELL)
Input Pad
G1 G2 SHIFT -D R
INPUT to internal logic
12 1 2 MUX
I.D . C od e bit C LO C K -D R Sc an C hain In
D C
12 12
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Figure 30
- Output Cell (OUT_CELL)
Sc an C hain O ut
EXTEST O U T P UT o r E nable from s ystem logic IDCO DE SHIFT -D R
G1 1 G1 G2 12 1 2 MUX D C D C 1 MUX
O U TP UT or E nable
I.D. code bit CLO CK -D R UPD AT E-DR
12 12
Sc an C hain In
Figure 31
- Bi-directional Cell (IO_CELL)
Scan C hain O ut IN PUT to internal logic
EXTE ST O U TPU T from internal logic ID C O D E SHIF T -D R IN P UT from pin
G1 1 G1 G2 12 1 2 MUX D C D C 1 MUX
O U T PU T to pin
I.D. code bit CLO CK -D R UPD AT E-DR
12 12
Sc an C hain In
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Figure 32
- Layout of Output Enable and Bi-directional Cells
S can C hain O ut
O U T P U T E N AB LE from internal logic (0 = drive) IN P U T to internal logic O U TP U T from internal logic
O U T _C E LL
IO _C E LL
I/O PAD
S can C hain In
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13
FUNCTIONAL TIMING All functional timing diagrams assume that polarity control is not being applied to input and output data and clock lines (i.e. polarity control bits in the S/UNI-QJET registers are set to their default states). Figure 33
R C LK [x]
- Receive DS1 Stream
R D A T I[x]
F BIT
IN F O 1
IN F O 2
IN F O 3
IN F O 4
IN F O 192
F B IT
IN F O 1
IN F O 2
IN F O 3
IN F O 4
IN F O 5
R O H M [x]
The Receive DS1 Stream diagram (Figure 33) shows the expected DS1 overhead indicators on ROHM[x] when the S/UNI-QJET is configured for DS1 PLCP or DS1 direct-mapped frame formats. Frame pulses on ROHM[x] are not required to be present. Once internally synchronized by a pulse on ROHM[x], the S/UNI-QJET can use its internal timeslot counter for DS1 overhead bit identification. The ATM cell stream is contained in RDATI[x], along with a framing bit placeholder every 193 bit periods. An upstream DS1 framer (such as the PM4341A T1XC or PM4344 TQUAD) must be used to identify the DS1 framing bit position. Figure 34
R C LK [x]
- Receive E1 Stream
R D A T I[x]
TS0 bit1
TS0 bit2
TS0 bit3
TS0 bit4
TS 0 bit5
TS 31 bit8 TS 0 bit1
TS 0 bit2
TS 0 bit3
TS 0 bit4
TS 0 bit5
TS 0 bit6
R O H M [x]
The expected Receive E1 Stream for direct-mapped or PLCP applications is shown in Figure 34. Frame pulses on ROHM[x] are not required to be present every frame. Once internally synchronized by a pulse on ROHM[x], the S/UNI-QJET can use its internal timeslot counter for E1 overhead bit identification. The ATM cell stream is contained in RDATI[x], along with a framing bit placeholder every 256 bit periods. An upstream E1 framer (such as the
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PM6341A E1XC or PM6344 EQUAD) must be used to identify the E1 framing bit position. Figure 35
R C LK [x]
LC V
- Receive Bipolar DS3 Stream
R P O S [x]
3 co nsec 0s
R N E G [x]
The Receive Bipolar DS3 Stream diagram (Figure 35) shows the operation of the S/UNI-QJET while processing a B3ZS encoded DS3 stream on inputs RPOS[x] and RNEG[x]. It is assumed that the first bipolar violation (on RNEG[x]) illustrated corresponds to a valid B3ZS signature. A line code violation is declared upon detection of three consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid B3ZS signature. Figure 36
R C LK [x]
- Receive Unipolar DS3 Stream
R D A T I[x]
X1 BIT
IN F O 1
IN F O 84
X2 BIT
IN F O 84
C B IT
IN F O 1
IN F O 2
IN F O 3
IN F O 4
IN F O 5
O R P O R M B IT
O R F B IT
LC V IN D IC A TIO N
R LC V [x]
The Receive Unipolar DS3 Stream diagram (Figure 36) shows the complete DS3 receive signal on the RDATI[x] input. Line code violation indications, detected by an upstream B3ZS decoder, are indicated on input RLCV[x]. RLCV[x] is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV[x].
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Figure 37
- Receive Bipolar E3 Stream
HD B3 S ig nature P atte rn
X 0 0 V
R C LK [x] R P O S [x]
LC V 4 con se c 0 s 0 0 0 V B 0 0 V
R N E G [x]
The Receive Bipolar E3 Stream diagram (Figure 37) shows the operation of the S/UNI-QJET while processing an HDB3-encoded E3 stream on inputs RPOS[x] and RNEG[x]. It is assumed that the first bipolar violation (on RNEG[x]) illustrated corresponds to a valid HDB3 signature. A line code violation is declared upon detection of four consecutive zeros in the incoming stream, or upon detection of a bipolar violation which is not part of a valid HDB3 signature. Figure 38
R C LK [x]
- Receive Unipolar E3 Stream
R D A T I[x]
F A1 1
F A1 2
IN F O X IN F O X +1
IN F O N
IN F O N +1 IN F O N +2 IN F O N +3 IN F O N +4 IN F O N +5 IN F O N +6 LC V IN D IC A TIO N
R LC V [x]
The Receive Unipolar E3 Stream diagram (Figure 38) shows the unipolar E3 receive signal on the RDATI[x] input. Line code violation indications, detected by an upstream HDB3 decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
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Figure 39
- Receive Bipolar J2 Stream
8 ze ro s
0 V 1 V 0 0 0 0 0 0 0 0 1 0 0 0 0 0
B 8 Z S sig natu re
0 0 0 V 1
R C L K [x] R P O S [x] R N E G [x]
LC V EXZ
The Receive Bipolar J2 Stream diagram (Figure 39) shows the operation of the S/UNI-QJET while processing a B8ZS-encoded J2 stream on inputs RPOS and RNEG. It is assumed that the first bipolar violation (on RNEG) illustrated corresponds to a valid B8ZS signature. A line code violation is declared upon detection of a bipolar violation which is not part of a valid B8ZS signature. An excessive zeros indication is given when 8 or more consecutive zeros are detected. Figure 40
R C LK [x]
- Receive Unipolar J2 Stream
R D A T I[x]
e1
e2
IN F O X IN F O X +1
IN F O N
IN F O N +1 IN F O N +2 IN F O N +3 IN F O N +4 IN F O N +5 IN F O N +6 LC V IN D IC A TIO N
R LC V [x]
The Receive Unipolar J2 Stream diagram (Figure 40) shows the unipolar J2 receive signal on the RDATI[x] input. Line code violation indications, detected by an upstream B8ZS decoder, are indicated on input RLCV. RLCV is sampled each bit period. The PMON Line Code Violation Event Counter is incremented each time a logic 1 is sampled on RLCV.
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Figure 41
R C LK [x]
- Generic Receive Stream
R D A T I[x]
O verhe ad O verhe ad O ver head O ver head O ver head O v erhead O ver head O verhe ad Bit 1 Bit 2 Bit 3 Bit 4 B it 5 B it 6 B it 7 B it 8
IN F O 1
IN F O 2
IN F O 3
IN F O 4
IN F O 5
R O H M [x]
The generic receive stream diagram (Figure 41) illustrates how ROHM is used to mark the location of the transmission system overhead bits in the RDATI[x] stream. RDATI[x] and ROHM[x] are both sampled on the rising edge of RCLK[x]. Figure 42 - Receive DS3 Overhead
D S 3 M -fram e P eriod
R O H F P [x] R O H C LK [x]
R O H C LK [x]
R O H [x]
X1
U nused
C1
U nused
C2
U nused
C3
R O H F P [x]
The Receive DS3 Overhead diagram (Figure 42) shows the extraction of the DS3 overhead bits on the ROH output, along with overhead clock (ROHCLK), and M-frame position indicator (ROHFP). The DS3 M-frame can be divided into seven M-subframes, with each subframe containing eight overhead bits. The table below illustrates the overhead bit order on ROH:
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Table 39
- DS3 Receive Overhead Bits DS3 Overhead Bits 1 2 N/U N/U N/U N/U N/U N/U N/U 3 C1 C1 C1 C1 C1 C1 C1 4 N/U N/U N/U N/U N/U N/U N/U 5 C2 C2 C2 C2 C2 C2 C2 6 N/U N/U N/U N/U N/U N/U N/U 7 C3 C3 C3 C3 C3 C3 C3 8 N/U N/U N/U N/U N/U N/U N/U
M-subframe
1 2 3 4 5 6 7
X1 X2 P1 P2 M1 M2 M3
The DS3 framing bits (F-bits) are not extracted on the overhead port. The bit positions corresponding to the F-bits in the extracted stream are marked N/U in the above table. The ROH stream is invalid when the DS3 frame alignment is lost. Figure 43 - Receive G.832 E3 Overhead
G .832 F ram e P eriod
R O H FP [x] R O H C LK [x] R O H [x]
FA1 FA2 EM TR MA NR GC FA1 FA2
54 cycles
R O H FP [x] R O H C LK [x]
bit 2 bit 5 bit 7 bit 2 bit 4 bit 7 bit 1 bit 4 bit 6 bit 1 bit 3 bit 4 bit 6 bit 8 bit 1 bit 3 bit 5 bit 6 bit 8 bit 2 bit 3 bit 5 bit 7 bit 8 bit 1
R O H [x]
FA 1 byte
FA 2 b yte
EM byte
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The Receive G.832 E3 Overhead diagram (Figure 43) shows the extraction of the G.832 E3 overhead bits on the ROH output, along with overhead clock (ROHCLK), and frame position indicator (ROHFP). Figure 44 - Receive G.751 E3 Overhead
G .751 F ra m e P eriod
R O H FP [x] R O H C LK [x] R O H [x]
RAI Nat C11 C21 C31 C41 C12 C22 C32 C42 C13 C23 C33 C43 J1 J2 J3 J4
... ... ...
30 cycles
RAI
Justification s ervic e bits and tributary justification bits output if P YLD &JU ST bit equals 0
The Receive G.751 E3 Overhead diagram (Figure 44) shows the extraction of the G.751 E3 overhead bits on the ROH output, along with overhead clock (ROHCLK), and frame position indicator (ROHFP). The justification indication bits (Cjk) along with the justification opportunity bits (J1-J4) are extracted when they are treated as overhead (PYLD&JUST bit in the E3 FRMR Maintenance Options register set to logic 0). Figure 45 - Receive J2 Overhead
T S 97 R CLK[x] R O H[x] 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7
1 1 0 0 m
T S 98
F-bits
TS1
X
X
R O H FP[x] R O H C LK[x]
Fra m e 1 Fra m es 2,3,4
The Receive J2 Overhead diagram (Figure 45) shows the extraction of the J2 overhead bits on the ROH output, along with overhead clock (ROHCLK), and frame position indicator (ROHFP). ROHCLK is a gapped clock with a maximum instantaneous rate equal to the RCLK frequency. ROHFP pulses on the first bit of TS97 in the first frame of each J2 multiframe.
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Figure 46
R P O H FP [x]
- Receive PLCP Overhead
F1 octet
B1 octet
G1 octet
M2 octe t
M1 octet
Z2 octet
Z1 octe t
R P O H C LK [x]
R P O H C LK [x]
B 8 B 1 BB 23 BBB 456 B 7 B 8 BBBBBB 234567
B 1 O c te t
R P O H [x]
B 1
B 8
B 1
F1 O cte t
R P O H FP [x]
The Receive PLCP Overhead diagram (Figure 46) shows the extraction of the PLCP path overhead bits on the RPOH output, along with overhead clock (RPOHCLK), and PLCP frame position indicator (RPOHFP). The path overhead octets are shifted out in order with the most significant bit (bit 1) of each octet first. The number of growth octets (Zn) in the PLCP frame varies according to the selected PLCP frame format (DS3, DS1, G.751 E3, or E1). The PLCP frame position indicator (RPOHFP) is set high once per PLCP frame period, during bit 1 of the F1 octet, and indicates the 8 kHz receive PLCP frame timing.
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Figure 47
T IC LK [x] T C LK [x]
- Transmit DS1 Stream
T D A T O [x]
F ram in g Position
O ctet 1 Bit 1
O ctet 24 B it 5
O ctet 24 B it 6
O ctet 24 O ctet 24 B it 7 B it 8
O verhe ad Slot
O ctet 1 Bit 1
T O H M [x]
The Transmit DS1 Stream diagram (Figure 47) illustrates the generation of DS1 overhead indicators on TOHM when the S/UNI-QJET is configured for DS1 PLCP or non-PLCP frame formats. The S/UNI-QJET flywheels using its internal timeslot counter to generate TOHM. The ATM cell stream is inserted in TDATO, along with a framing bit placeholder every 193 bit periods. An upstream DS1 framer (such as the PM4341A T1XC or PM4344 TQUAD) must be used to insert the appropriate DS1 framing pattern. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 48
T IC LK [x] T C LK [x]
- Transmit E1 Stream
T D A T O [x]
TS0 bit 1
TS 0 bit 2
TS 31 bit 5 TS 31 bit 6 TS 31 bit 7 TS31 bit 8 TS 0 bit 1 TS0 bit 2
T O H M [x]
The Transmit E1 Stream diagram (Figure 48) illustrates the generation of E1 frame alignment indicators on TOHM when the S/UNI-QJET is configured for E1 PLCP or non-PLCP frame formats. The S/UNI-QJET flywheels using its internal timeslot counter to generate TOHM. The ATM cell stream is inserted in TDATO, along with a framing bit placeholder every 256 bit periods. An upstream E1 framer (such as the PM6341A E1XC or PM6344 EQUAD) must be used to insert the appropriate E1 framing pattern. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
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Figure 49
- Transmit Bipolar DS3 Stream
T IC LK [x] T C LK [x] T P O S [x]
T N E G [x]
1 1 0 0 0 1 0
The Transmit Bipolar DS3 Stream diagram (Figure 49) illustrates the generation of a bipolar DS3 stream. The B3ZS encoded DS3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a DS3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 50
T IC LK [x] T C LK [x]
N ib 1 B it 4 N ib 21 B it 1 N ib 22 B it 4 N ib 1190 B it 1 N ib 1 B it 4
- Transmit Unipolar DS3 Stream
T D A T O [x]
X1
X2
X1
T O H M [x]
The Transmit Unipolar DS3 Stream diagram (Figure 50) illustrates the unipolar DS3 stream generation. The ATM cell stream, along with valid DS3 overhead bits is contained in TDATO. The TOHM output marks the M-frame boundary (the X1 bit) in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
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Figure 51
- Transmit Bipolar E3 Stream
H D B3 S ig nature P attern
X 0 0 V
T IC LK [x] T C LK [x] T P O S [x]
B 0 0 V
T N E G[x]
0
0
0
V
The Transmit Bipolar E3 Stream diagram (Figure 51) illustrates the generation of a bipolar E3 stream. The HDB3 encoded E3 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a E3 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 52
T IC LK [x] T C LK [x]
- Transmit Unipolar E3 Stream
T D A T O [x]
IN F O X
IN F O X+ 1
F A1 1
F A 12
F A 13
IN F O X+ 465
BIP[0]
BIP[1]
BIP[2]
BIP[3]
BIP[4]
BIP[5]
T O H M [x]
The Transmit Unipolar E3 Stream diagram (Figure 52) illustrates the unipolar E3 stream generation. The ATM cell stream, along with valid E3 overhead bits is contained in TDATO. The TOHM output shown marks the G.832 frame boundary (the first bit of the FA1 frame alignment byte) in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
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Figure 53
- Transmit Bipolar J2 Stream
B 8 Z S s ig n a tu re
0 0 0 V 1 0 V 1 1 0 0 0 0 0 0 0 1 1 0 0 0 0 0
T IC L K [x] T C L K [x] T P O S [x] T N E G [x]
The Transmit Bipolar J2 Stream diagram (Figure 53) illustrates the generation of a bipolar J2 stream. The B8ZS encoded J2 stream is present on TPOS and TNEG. These outputs, along with the transmit clock, TCLK, can be directly connected to a J2 line interface unit. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals. Figure 54
T IC LK [x] T C LK [x]
- Transmit Unipolar J2 Stream
T D A T O [x]
e4
e5
bit1
bit 2
bit 3
bit 782
bit 783
bit 784
1
1
0
0
fram e align m ent signal
T O H M [x]
The Transmit Unipolar J2 Stream diagram (Figure 54) illustrates the unipolar J2 stream generation. The ATM cell stream, along with valid J2 overhead bits is contained in TDATO. The TOHM output shown marks the J2 multi-frame boundary (the first frame-alignment bit of each J2 multi-frame) in the transmit stream. Note that TCLK is a flow through version of TICLK; a variable propagation delay exists between these two signals.
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Figure 55
T IC L K b it log ic 0:
- Generic Transmit Stream
T IO H M [x] T IC L K [x] T C LK [x] T D A T O [x]
Bit 5
Bit 6
Bit 7
Bit 8
Overh ead Placehold er Bits
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
A TM C e ll Octe t n
A TM C e ll Octet n +1
T O H M [x]
T IC L K b it log ic 1:
T IO H M [x]
T IC L K [x]
T D A T O [x]
Bit 3
Bit 4
Bit 5
Bit 6
Bit 7
Bit 8
Overh ead Placehold er Bits
Bit 1
Bit 2
Bit 3
Bit 4
Bit 5
A TM C e ll Octe t n
T O H M [x]
A TM C e ll Octet n +1
The Generic Transmit Stream diagram (Figure 55) illustrates overhead indication positions when interfacing to a non-PLCP based transmission system not supported by the SUNI-QJET. The overhead bit placeholder positions are indicated using the TIOHM input. The ATM cells presented in the TDATO transmit stream are held off to include the overhead placeholders. The location of these placeholder positions is indicated by TOHM. A downstream framer inserts the correct overhead information in the placeholder positions. The delay between TIOHM and TOHM is dependent on the state of the TICLK bit of the S/UNI-QJET Transmit Configuration register. If the TICLK bit is a logic zero, TOHM is updated on the falling TCLK edge. TCLK is a flow-through version of TICLK and the propagation delay between TICLK and TCLK may vary depending on specific configurations. If the TICLK bit is a logic one, TOHM is presented on the fifth rising edge of TICLK after the rising edge which samples TIOHM.
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Figure 56
- Transmit DS3 Overhead
D S 3 M -fram e P e rio d
T O H FP [x]
T O H C LK [x]
T O H C LK [x]
T O H FP [x]
T O H [x]
X1
F1
C1
F2
C2
F3
C3
T O H IN S [x]
The Transmit DS3 Overhead diagram (Figure 56) shows the insertion of DS3 overhead bits using the TOH input, along with the overhead insertion enable input, TOHINS. The TOHFP output is set to logic 1 once per DS3 M-frame period (during the X1 bit position). In Figure 56, the data sampled on TOH during the X1, C1, F2, and C2 bit positions is inserted into the DS3 overhead bits in the transmit stream. The F1, F3, and C3 overhead bits are internally generated by the S/UNI-QJET. The table below illustrates the overhead bit order on TOH: Table 40 - DS3 Transmit Overhead Bits DS3 Overhead Bits 1 1 2 3 X1 X2 P1 2 F1 F1 F1 3 C1 C1 C1 4 F2 F2 F2 5 C2 C2 C2 6 F3 F3 F3 7 C3 C3 C3 8 F4 F4 F4
M-subframe
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M-subframe
DS3 Overhead Bits 1 2 F1 F1 F1 F1 3 C1 C1 C1 C1 4 F2 F2 F2 F2 5 C2 C2 C2 C2 6 F3 F3 F3 F3 7 C3 C3 C3 C3 8 F4 F4 F4 F4
4 5 6 7 Figure 57
P2 M1 M2 M3
- Transmit G.832 E3 Overhead
G .832 F ram e P erio d
T O H FP [x] T O H C LK [x] T O H [x] T O H IN S [x]
54 cycles
FA1 FA2 EM TR MA NR GC FA1 FA2
T O H FP [x] T O H C LK [x]
bit 2 bit 3 bit 4 bit 5 bit 7 bit 8 bit 1 bit 2 bit 4 bit 5 bit 6 bit 7 bit 1 bit 2 bit 3 bit 4 bit 6 bit 7 bit 8 bit 1 bit 6 bit 3 bit 8 bit 5 bit 1
T O H [x]
FA 1 b yte
FA 2 b yte
EM byte
T O H IN S [x]
The Transmit G.832 E3 Overhead diagram (Figure 57) shows the insertion of G.832 E3 overhead bits using the TOH input, along with the overhead insertion enable input, TOHINS. The TOHFP output is set to logic 1 once per G.832 frame period (during the first bit position of the FA1 byte). In Figure 57, the bit data sampled on TOH during each byte position while TOHINS is logic 1 is inserted into the G.832 E3 overhead bits in the transmit stream. Note that if an entire byte is to be replaced with data from the TOH stream, TOHINS must be held logic 1 for the duration of that byte position. Also note that the EM byte behaves as an
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error mask, that is the binary value sampled on TOH in the EM byte location is not inserted directly into the transmit overhead but, rather, the value is XORed with the calculated BIP-8 and inserted in the transmit overhead. Asserting TOHINS during the "gaps" in the TOH stream has no effect. Figure 58 - Transmit G.751 E3 Overhead
G .751 F ram e P erio d
T O H FP [x] T O H C LK [x] T O H [x] T O H IN S [x]
RAI Nat C11 C21 C31 C41 C12 C22 C32 C42 C13 C23 C33 C43 J1 J2 J3 J4
... ... ... ...
30 cycles
RAI
The Transmit G.751 E3 Overhead diagram (Figure 58) shows the insertion of G.751 overhead bits RAI, the National Use Bit, and the stuff indication and opportunity bits using the TOH input, along with the overhead insertion enable input, TOHINS. The TOHFP output is set to logic 1 once per G.751 E3 frame period (during the RAI bit position). In Figure 58, the data sampled on TOH during the RAI, National Use, or stuff bit positions while TOHINS is logic 1 is inserted into the G.751 E3 overhead bits in the transmit stream. The PYLD&JUST bit in the E3 TRAN Status and Diagnostics Options register has no affect on the insertion of the justification service and the tributary justification bits through the TOH and the TOHINS inputs. Figure 59 - Transmit J2 Overhead
J2 M ulti-Fra m e P eriod
T O H FP[x]
T O H CL K [x]
T O H [x]
1
1
0
0
m1
T O H IN S[x]
... ... ... ...
T S9 7 T S9 8
e1
e2
e3
e4
e5
... ... ... ...
T S9 7
T S9 7
T S9 8
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The Transmit J2 Overhead diagram (Figure 59) shows the insertion of J2 overhead bits using the TOH and TOHINS inputs. The TOHFP output is set to logic 1 once per J2 multiframe (for the first bit of TS97 in the first frame of the J2 multiframe). TOHCLK is a gapped clock which will pulse at a maximum instantaneous rate equal to the TICLK frequency. When TOHINS is a logic 1, the TOH input pin state replaces that generated within the J2 TRAN block. TOH and TOHINS are sampled on the rising TOHCLK clock edge. Figure 60
T P O H FP [x]
- Transmit PLCP Overhead
F1 octet
B1 octet
G1 octet
M2 octet
M1 octet
Z2 octet
Z1 octet
T P O H C LK [x]
T P O H C LK [x]
B 8 B 1 BBBBBBB 2345678
F1 O ctet
T P O H[x]
Don't C are
B 1 O c te t
B 1
T P O H FP [x]
T P O H IN S [x]
The Transmit PLCP Overhead diagram (Figure 60) shows the insertion of the PLCP path overhead bits using the TPOH input, along with overhead clock (TPOHCLK), and PLCP frame position indicator (TPOHFP). The path overhead octets are shifted in order with the most significant bit (bit 1) of each octet first. The number of growth octets (Zn) in the PLCP frame varies according to the
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selected PLCP frame format (DS3, DS1, G.751 E3, or E1). The PLCP frame position indicator (TPOHFP) is set high once per PLCP frame period, during bit 1 of the F1 octet, and indicates the transmit PLCP frame timing. TPOH and TPOHINS are sampled using the rising edge of TPOHCLK. The bit presented on TPOH is only inserted into the path overhead if TPOHINS is asserted during the bit in question, or if the appropriate bit is set in the SPLT Control Register. The timing diagram above assumes that the SRCB1 bit in the SPLT Control Register is programmed to logic 0, thereby selecting internal insertion of that octet. Figure 61
T IC LK [x]
- Framer Mode DS3 Transmit Input Stream
T D A T I[x]
IN F O 82
IN F O 83
IN F O 84
F4
IN F O 82
IN F O 83
IN F O 84
X1
IN F O 1
IN F O 2
X2
IN F O 1
IN F O 2
IN F O 3
IN F O 82
IN F O 83
IN F O 84
T F PI/T M FP I[x] T F PO /T M FP O [x]
Figure 62
T IC LK [x]
- Framer Mode DS3 Transmit Input Stream With TGAPCLK
T G A P C LK [x] T DA T I[x]
IN F O 8 3
IN F O 8 4
IN F O 1
IN F O 8 3
IN F O 8 4
IN F O 1
IN F O 2
IN F O 3
IN F O 1
IN F O 2
IN F O 3
IN F O 4
IN F O 8 1
IN F O 8 2
IN F O 8 3
The Framer Mode DS3 Transmit Input Stream diagrams (Figure 61 and Figure 62) show the expected format of the inputs TDATI and TFPI/TMFPI along with TICLK and the output TFPO/TMFPO when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set, and the S/UNI-QJET is configured for the DS3 transmit format. If the TXMFPI register bit is logic 0, then TFPI is valid, and the S/UNI-QJET will expect TFPI to pulse for every DS3 overhead bit with alignment to TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid, and the S/UNI-QJET will expect TMFPI to pulse once every DS3 M-frame with alignment to TDATI. If the TXMFPO register bit is logic 0, then TFPO is valid, and the S/UNI-QJET will pulse TFPO once every 85 TICLK cycles, providing upstream equipment with a reference DS3 overhead pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the S/UNI-QJET will pulse TMFPO once every 4760 TICLK cycles, providing upstream equipment with a reference M-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the S/UNI-QJET
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Configuration 2 register is set to logic 1, as in Figure 62. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK. Figure 63
R S C LK [x] R D A T O [x]
- Framer Mode DS3 Receive Output Stream
IN F O 82
IN F O 83
IN F O 84
F4
IN F O 82
IN F O 83
IN F O 84
X1
IN F O 1
IN F O 2
X2
IN F O 1
IN F O 2
IN F O 3
IN F O 82
IN F O 83 IN F O 84
R F P O /R M FP O [x] R O V R H D [x]
Figure 64
R G A P C LK [x] R D A T O [x]
- Framer Mode DS3 Receive Output Stream with RGAPCLK
IN F O 8 2
IN F O 8 3
IN F O 8 4
IN F O 8 2
IN F O 8 3
IN F O 8 4
IN F O 1
IN F O 2
IN F O 8 4
IN F O 1
IN F O 2
IN F O 3
IN F O 8 2
IN F O 8 3 IN F O 8 4
The Framer Mode DS3 Receive Output Stream diagrams (Figure 63 and Figure 64) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set. Figure 63 shows the data streams when the S/UNI-QJET is configured for the DS3 receive format. If the RXMFPO and 8KREFO register bits are logic 0, RFPO is valid and will pulse high for one RSCLK cycle on first bit of each M-subframe with alignment to the RDATO data stream. If the RXMFPO register bit is a logic 1 (as shown in Figure 63) and the 8KREFO register bit is logic 0, RMFPO is valid and will pulse high on the X1 bit of the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. As shown in Figure 64 the RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1. RGAPCLK remains high during the overhead bit positions and RDATO does not change. Figure 65
T IC LK [x] T D A T I[x]
- Framer Mode G.751 E3 Transmit Input Stream
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
1
1
1
1
0
1
0
0
0
0
RAI
Nat
bit13
T FP I/T M FP I[x] T FP O /T M FP O [x]
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Figure 66
TICL K[x] TG AP C LK [x] T D A T I[x]
- Framer Mode G.751 E3 Transmit Input Stream With TGAPCLK
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
bit13
bit14
The Framer Mode G.751 E3 Transmit Input Stream diagrams (Figure 65 and Figure 66) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set, and the S/UNI-QJET is configured for the E3 G.751 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the frame alignment signal in the G.751 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 1536 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1, as in Figure 66. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK. Figure 67
R S C LK [x] R D A T O [x]
- Framer Mode G.751 E3 Receive Output Stream
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
1
1
1
1
0
1
0
0
0
0
RAI
N at
bit13
R FP O /R M FP O [x] R O V R H D [x]
Figure 68 RGAPCLK
R G A P C LK [x] R D A T O [x]
- Framer Mode G.751 E3 Receive Output Stream with
bit 1529
bit 1530
bit 1531
bit 1532
bit 1533
bit 1534
bit 1535
bit 1536
bit13
The Framer Mode G.751 E3 Receive Output Stream diagrams (Figure 67 and Figure 68) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the FRMRONLY and the 8KREFO bits in the
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S/UNI-QJET Configuration 1 register are set to logic 1 and logic 0 respectively. Figure 67 shows the data streams when the S/UNI-QJET is configured for the E3 G.751 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the framing alignment signal in the G.751 E3 output data stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. If the PYLD&JUST register bit in the E3 FRMR Maintenance Options register is set to logic 0, the Cjk and Pk bits in the RDATO stream will be marked as overhead bits. If the PYLD&JUST register bit is set to logic 1, the Cjk and Pk bits in the RDATO stream will be marked as payload. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 68. Figure 69
TICL K[x] T D A T I[x]
- Framer Mode G.832 E3 Transmit Input Stream
O ct 530
1
O ct 530
2
O ct 530
3
O ct 530
4
O ct 530
5
O ct 530
6
O ct 530
7
O ct 530
8
FA 1 1 FA 1 2
FA 1 3 FA 1 4 FA 1 5
FA 1 6 FA 1 7 FA 1 8
O ct N 1
O ct N 2
O ct N 3
T F P I/T M FP I[x] T F P O /T M F P O [x]
Figure 70
T ICLK [x] T G A P CL K [x] T DA T I[x]
- Framer Mode G.832 E3 Transmit Input Stream With TGAPCLK
O c t 53 0 1
O c t 53 0 2
O c t 53 0 3 O c t 53 0 4
O c t 53 0 5 O c t 53 0 6
O ct 53 0 7
O ct 53 0 8
O ct N 1
O ct N 2
O c t N3
The Framer Mode G.832 E3 Transmit Input Stream diagrams (Figure 69 and Figure 70) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set, and the S/UNI-QJET is configured for the E3 G.832 transmit format. TFPI or TMFPI pulses high for one TICLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 input data stream on TDATI. TFPO or TMFPO will pulse high for one out of every 4296 TICLK cycles, providing upstream equipment with a reference frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the S/UNI-QJET Configuration 2
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register is set to logic 1, as in Figure 70. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK. Figure 71
R S CL K[x] R D AT O [x] R FP O /R M FP O [x] R O V R HD [x]
- Framer Mode G.832 E3 Receive Output Stream
O ct 530
1
O ct 530
2
O ct 530
3
O ct 530
4
O ct 530
5
O ct 530
6
O ct 530
7
O ct 530
8
FA 1 1 FA 1 2
FA 1 3 FA 1 4 FA 1 5
FA 1 6 FA 1 7 FA 1 8
FA 2 8
O ct 1 1
O ct 1 2
Figure 72 RGAPCLK
RG A P C LK [x] RD A T O [x]
- Framer Mode G.832 E3 Receive Output Stream with
O c t 53 0 1 O c t 53 0 2
O c t 53 0 3
O c t 53 0 4 O c t 53 0 5 O c t 53 0 6 O ct 53 0 7
O ct 53 0 8
O ct 1 1
O c t 12
The Framer Mode G.832 E3 Receive Output Stream diagrams (Figure 71 and Figure 72) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set. Figure 71 shows the data streams when the S/UNI-QJET is configured for the E3 G.832 receive format. RFPO or RMFPO pulses high for one RSCLK cycle and is aligned to the first bit of the FA1 byte in the G.832 E3 output data stream on RDATO. ROVRHD will be high for every overhead bit position on the RDATO data stream. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 72. Figure 73
T IC LK [x] T D A T I[x]
- Framer Mode J2 Transmit Input Stream
TS98
6
TS98
7
TS98
8
e1
TS98
6
TS98
7
TS98
8
1
1
0
TS98
8
x1
x2
x3
TSN
6
TSN
7
TSN
8
T F PI/T M FP I[x] T F PO /T M FP O [x]
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Figure 74
T ICLK [x] T G A P CL K [x] T DA T I[x]
- Framer Mode J2 Transmit Input Stream With TGAPCLK
TS 9 8
7
TS 9 8
8
TS 1
1
TS 9 8
7
TS 9 8
8
TS 1
1
TS 9 8
8
TS 1
1
TS N
6
TS N
7
TSN
8
The Framer Mode J2 Transmit Input Stream diagrams (Figure 73 and Figure 74) show the expected format of the inputs TDATI, TFPI/TMFPI, and TICLK and the output TFPO/TMFPO (and TGAPCLK) when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set, and the S/UNI-QJET is configured for the J2 transmit format. If the TXMFPI register bit is logic 0, then TFPI is valid (as shown in Figure 73). The S/UNI-QJET will expect TFPI to pulse once every J2 frame with alignment to the first frame alignment bit on TDATI. If the TXMFPI register bit is logic 1, then TMFPI is valid. The S/UNI-QJET will expect TMFPI to pulse once every J2 multi-frame with alignment to the first frame alignment bit on TDATI. If the TXMFPO register bit is logic 0, then TFPO is valid. The S/UNI-QJET will pulse TFPO once every 789 TICLK cycles, providing upstream equipment with a reference frame pulse. If the TXMFPO register bit is logic 1, then TMFPO is valid and the S/UNI-QJET will pulse TMFPO once every 3156 TICLK cycles, providing upstream equipment with a reference multi-frame pulse. The alignment of TFPO or TMFPO is arbitrary. There is no set relationship between TFPO/TMFPO and TFPI/TMFPI. The TGAPCLK output is available in place of TFPO/TMFPO when the TXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1, as in Figure 74. TGAPCLK remains high during the overhead bit positions. TDATI is sampled on the falling edge of TGAPCLK. Figure 75
R S C LK [x] R D A T O [x]
- Framer Mode J2 Receive Output Stream
TS97
6
TS97
7
TS97
8
e1
1
1
0
0
m1
TS1
1
TS96
8
TS97
1
TS97
2
TS97
3
TS97
6
TS97
7
TS97
8
R FP O /R M FP O [x] R O V R H D [x]
Figure 76
RG A P C LK [x] RD A T O [x]
- Framer Mode J2 Receive Output Stream with RGAPCLK
TS 9 6
6
TS 9 6
7
TS 9 6 8
TS 9 6 8
TS 1
1
TS 9 6
8
TS 9 0
6
TS 9 0
7
TS9 0
8
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The Framer Mode J2 Receive Output Stream diagrams (Figure 75 and Figure 76) show the format of the outputs RDATO, RFPO/RMFPO, RSCLK (and RGAPCLK), and ROVRHD when the FRMRONLY bit in the S/UNI-QJET Configuration 1 register is set. Figure 75 shows the data streams when the S/UNI-QJET is configured for the J2 receive format. If the RXMFPO register bit is a logic 0, RFPO is valid and will pulse high for one RSCLK cycle once each J2 frame with alignment to the first frame alignment bit on the RDATO data stream (as shown in Figure 75). If the RXMFPO register bit is a logic 1, RMFPO is valid and will pulse high once each J2 multi-frame aligned to the first frame alignment bit on the RDATO data output stream. ROVRHD will be high for every overhead bit position on the RDATO data stream. The RGAPCLK output is available in place of RSCLK when the RXGAPEN bit in the S/UNI-QJET Configuration 2 register is set to logic 1. RGAPCLK remains high during the overhead bit positions as shown in Figure 76. Figure 77 - Multi-PHY Polling and Addressing Transmit Cell Interface
T FC LK
DT CA [D]
TC A LE V EL0= 0
TCA
C A(A)
C A(B)
C A(C )
X
C A(B)
C A(A)
TENB
T A D R[4:0] TSOC
A
1Fh
B
1Fh
C
1Fh
X
B
1Fh
A
1Fh
C
T D A T [15:0]
W (n-7) W (n-6)
W (n-5) W (n-4) W (n-3)
W (n-2) W (n-1)
W (n)
X
X
W1
W2
W3
W4
TPRTY
Figure 77 is an example of the multi-PHY polling and selection sequence supported by the S/UNI-QJET. "A", "B", "C", and "D" represent any arbitrary address values of PHY devices which may be occupied by the S/UNI-QJET. The ATM Layer device is not restricted in its polling order. Initially PHY "D" is accepting a cell and the direct TCA for that PHY is shown as DTCA[D]. The effect
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of TCALEVEL0 is indicated with a dashed line in the figure. The PHY associated with address "A" indicates it cannot accept a cell, but PHY "B" indicates it is willing to accept a cell. As a result, the ATM Layer places address "B" on TADR[4:0] the cycle before TENB is asserted to select PHY "B" as the next cell destination. In this example, the PHY "C" status is ignored. The ATM Layer device is not constrained to select the latest PHY polled. As soon as the cell transfer is started, the polling process may be restarted. The data on TDAT (W1, W2, ...) may be 8-bit or 16-bits wide, depending on the setting of the ATM8 input. During multi-PHY operation, several PHY layer devices share the TCA signal. As a result, this signals must be tri-stated in all PHY devices which have not been selected for polling by the ATM Layer. The value of TADR[4:0] selects the PHY being polled for the TCA signal, and all devices not corresponding to this address must tri-state its TCA output. This multi-PHY operation is directly supported by the S/UNI-QJET. Figure 78 - Multi-PHY Polling and Addressing Receive Cell Interface
R FC LK
D R C A [D ] RCA
R C A LE V E L0 = 0
C A(A)
C A(B)
C A (C )
X
C A (B )
C A (D )
RENB
R A D R [4:0] RSOC
A
1Fh
B
1Fh
C
1Fh
X
B
1Fh
D
1Fh
E
R D A T [15:0] W (n-7)
W (n-6)
W (n-5) W (n-4)
W (n-3) W (n-2) W (n-1)
W (n)
W1
W2
W3
RPRTY
Figure 78 shows an example of the multi-PHY polling and selection sequence supported by the S/UNI-QJET. "A", "B", "C", "D", and "E" represent any arbitrary address values which may be occupied by the S/UNI-QJET. Initially cell data is
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being received from PHY "D," and the DRCA[D] signal shows how the DRCA[x] signals behave based on the value of the RCALEVEL0 register bit(s). The ATM Layer device is not restricted in its polling order. The PHY associated with address "A" indicates it does not have a cell available, but PHY "B" indicates that it does. As a result, the ATM Layer places address "B" on RADR[4:0] the cycle before RENB is asserted to select PHY "B" as the next cell source. In this example, PHY "C"s status is ignored. The ATM Layer device is not constrained to select the latest PHY polled. As soon as the cell transfer is started, the polling process may be restarted. The data on RDAT (W1, W2, ...) may be 8-bit or 16bits wide, depending on the setting of the ATM8 input. During multi-PHY operation, several PHY layer devices share the RDAT[15:0], RSOC, RPRTY, and RCA signals. As a result, these signals must be tri-stated in all PHY devices which have not been selected for reading or polling by the ATM Layer. Selection of which PHY layer device is being read is made by the value on RADR[4:0] the cycle before RENB is asserted and affects the RDAT[15:0], RSOC, and RPRTY signals. The value of RADR[4:0] selects the PHY being polled for the RCA signal, and all devices not corresponding to this address must tri-state its RCA output. These multi-PHY operations are directly supported by the S/UNI-QJET.
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14
ABSOLUTE MAXIMUM RATINGS Table 41 - Absolute Maximum Ratings -55C to +125C -65C to +150C -0.3V to 4.6V VDD - 0.3V to 5.5V -0.3 V to BIAS +0.3 V 1000 V 100 mA 20 mA +230C +150C
Ambient Temperature under Bias Storage Temperature Supply VDD with respect to GND Voltage on BIAS with respect to GND Voltage on Any Pin Static Discharge Voltage Latch-Up Current DC Input Current Lead Temperature Absolute Maximum Junction Temperature
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15
D.C. CHARACTERISTICS TC = -40C to +85C, VDD = 3.3V 10%, VDD < BIAS < 5.5V (Typical Conditions: TC = 25C, VDD = 3.3V, VBIAS = 5V) Table 42
Symbol VDD BIAS IBIAS VIL
- DC Characteristics
Parameter Power Supply 5V Tolerant Bias Current into 5V Bias Input Low Voltage 0 Min 2.97 VDD Typ 3.3 5.0 6.0 0.8 Max 3.63 5.5 Units Volts Volts A Volts VBIAS = 5.5V Guaranteed Input Low voltage. Conditions
VIH
Input High Voltage
2.0
BIAS
Volts
Guaranteed Input High voltage.
VOL
Output or Bi-directional Low Voltage
0.23
0.4
Volts
Guaranteed output Low voltage at VDD=2.97V and IOL=maximum rated for pad.
4, 5, 6
VOH
Output or Bi-directional High Voltage
2.4
2.93
Volts
Guaranteed output High voltage at VDD=2.97V and IOH=maximum rated current for pad.
4, 5, 6
VT-
Reset Input Low Voltage
0.8
Volts
Applies to RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, and REF8KI.
VT+
Reset Input High Voltage
2.0
Volts
Applies to RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, and REF8KI.
VTH
Reset Input Hysteresis Voltage
0.5
Volts
Applies to RSTB, TRSTB, TICLK[4:1], RCLK[4:1], TFCLK, RFCLK, TCK, TDI, TMS, and REF8KI.
1, 3
IILPU IIHPU IIL IIH CIN COUT
Input Low Current Input High Current Input Low Current Input High Current Input Capacitance Output Capacitance
-100 -10 -10 -10
-60 0 0 0 6 6
-10 +10 +10 +10
A A A A pF pF
VIL = GND.
VIH = VDD. VIL = GND.
1. 3
2, 3
VIH = VDD.
2, 3
tA=25C, f = 1 MHz tA=25C, f = 1 MHz
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Symbol CIO IDDOP1
Parameter Bi-directional Capacitance Operating Current
Min
Typ 6 299.1
Max
Units pF
Conditions tA=25C, f = 1 MHz VDD = 3.63V, Outputs Unloaded (DS3/PLCP mode)
375
mA
IDDOP2
Operating Current
12.2
30
mA
VDD = 3.63V, Outputs Unloaded (T1/E1 PLCP mode)
IDDOP3
Operating Current
301.3
375
mA
VDD = 3.63V, Outputs Unloaded (DS3 ATM mode)
IDDOP4
Operating Current
284.9
350
mA
VDD = 3.63V, Outputs Unloaded (E3 ATM mode)
IDDOP5
Operating Current
43.6
75
mA
VDD = 3.63V, Outputs Unloaded (J2 ATM mode)
IDDOP6
Operating Current
258.3
330
mA
VDD = 3.63V, Outputs Unloaded (52 Mbit/s arbitrary framing format with ATM direct mapping)
IDDOP7
Operating Current
268.3
330
mA
VDD = 3.63V, Outputs Unloaded (DS3 framer only)
IDDOP8
Operating Current
259.9
330
mA
VDD = 3.63V, Outputs Unloaded (E3 framer only)
IDDOP9
Operating Current
37.1
75
mA
VDD = 3.63V, Outputs Unloaded (J2 framer only)
Notes on D.C. Characteristics: 1. Input pin or bi-directional pin with internal pull-up resistor. 2. Input pin or bi-directional pin without internal pull-up resistor 3. Negative currents flow into the device (sinking), positive currents flow out of the device (sourcing). 4. The Utopia interface outputs, RDAT[15:0], RPRTY, RCA, DRCA[4:1], RSOC, TCA, and DTCA[4:1], have 12 mA drive capability. 5. The outputs TCLK[4:1], TPOS/TDATO[4:1], TNEG/TOHM[4:1], TPOHFP/TFPO/TMFPO/TGAPCLK[4:1], LCD/RDATO[4:1], RPOH/ROVRHD[4:1], RPOHCLK/RSCLK/RGAPCLK[4:1], and REF8KO/RPOHFP/RFPO/RMFPO[4:1] have 6 mA drive capability. 6. The data bus outputs, D[7:0], and all outputs not specified above have 3 mA drive capability.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
7. RFCLK and TFCLK are 3.3 V only input pins - they are not 5 V tolerant. Connecting a 5 V signal to these inputs may result in damage to the part.
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DATASHEET PMC-960835 ISSUE 6 SATURN QUAD USER NETWORK INTERFACE FOR J2, E3, T3
16
MICROPROCESSOR INTERFACE TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 3.3V 10%) Table 43 Symbol tSAR tHAR tSALR tHALR tVL tSLR tHLR tPRD tZRD tZINTH - Microprocessor Interface Read Access (Figure 79) Parameter Address to Valid Read Set-up Time Address to Valid Read Hold Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Read Set-up Latch to Read Hold Valid Read to Valid Data Propagation Delay Valid Read Negated to Output Tristate Valid Read Negated to Output Tristate Min 10 5 10 10 5 0 5 70 20 50 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 79
- Microprocessor Interface Read Timing
A [10:0] tS ALR tV L ALE
V a lid A d d r e s s
tH ALR tS LR tHLR
tS A R (C S B +R D B )
tH A R
tZ IN T H
tP R D D [7:0]
tZ R D
V a lid D a ta
Notes on Microprocessor Interface Read Timing: 1. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 2. Maximum output propagation delays are measured with a 100 pF load on the Microprocessor Interface data bus, (D[7:0]). 3. A valid read cycle is defined as a logical OR of the CSB and the RDB signals. 4. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALR, tHALR, tVL, tSLR, and tHLR are not applicable. 5. Parameter tHAR is not applicable if address latching is used.
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6. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 7. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. Table 44 Symbol tSAW tSDW tSALW tHALW tVL tSLW tHLW tHDW tHAW tVWR - Microprocessor Interface Write Access (Figure 80) Parameter Address to Valid Write Set-up Time Data to Valid Write Set-up Time Address to Latch Set-up Time Address to Latch Hold Time Valid Latch Pulse Width Latch to Write Set-up Latch to Write Hold Data to Valid Write Hold Time Address to Valid Write Hold Time Valid Write Pulse Width Min 10 20 10 10 5 0 5 5 5 40 Max Units ns ns ns ns ns ns ns ns ns ns
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Figure 80
- Microprocessor Interface Write Timing
A [1 0:0] tS A LW tV L ALE
V a lid A d d r e s s
tH A LW tS LW tHLW
tS A W (C S B +W R B )
tV W R
tH A W
tS DW D [7:0]
tH DW
V a lid D a ta
Notes on Microprocessor Interface Write Timing: 1. A valid write cycle is defined as a logical OR of the CSB and the WRB signals. 2. In non-multiplexed address/data bus architectures, ALE should be held high so parameters tSALW, tHALW, tVL, tSLW, and tHLW are not applicable. 3. Parameter tHAW is not applicable if address latching is used. 4. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock. 5. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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17
A.C. TIMING CHARACTERISTICS (TC = -40C to +85C, VDD = 3.3V 10%) Table 45 Symbol tVRSTB Figure 81 - RSTB Timing (Figure 81) Description RSTB Pulse Width4 - RSTB Timing
tVR S T B RSTB
Min
Typical Max 100
Units ns
Table 46 Symbol fTFCLK DTFCLK tSTFCLK
- Transmit ATM Cell Interface Timing (Figure 82) Description TFCLK Frequency TFCLK Duty Cycle TENB, TADR[4:0], TDAT[15:0], TPRTY, and TSOC Set-up time to TFCLK TENB, TADR[4:0], TDAT[15:0], TPRTY, and TSOC Hold time to TFCLK TFCLK High to DTCA[4:1] and TCA Valid TFCLK High to TCA Tri-state TFCLK High to TCA Driven 40 3 Min Max 52 60 Units MHz % ns
tHTFCLK
1
ns
tPTCA tZTCA tZBTCA
1 1 1
12 10
ns ns ns
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Figure 82
- Transmit ATM Cell Interface Timing
T FC LK tS TENB tH
T F C LK
T F C LK
tS
T F C LK
tH
T F C LK
T D A T [15:0] tS tH
T F C LK
T F C LK
TPRTY tS tH
T F C LK
T F C LK
TSOC
tP T C A D T C A [x]/T C A
tZ T C A TCA tZB T C A TCA
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Table 47 Symbol fRFCLK DRFCLK tSRFCLK tHRFCLK tPRFCLK tZRFCLK tZBRFCLK
- Receive ATM Cell Interface Timing (Figure 83) Description RFCLK Frequency RFCLK Duty Cycle RENB and RADR[4:0] Set-up time to RFCLK RENB and RADR[4:0] Hold time to RFCLK RFCLK High to Output Valid RFCLK High to Output Tri-state RFCLK High to Output Driven 40 3 1 1 1 1 12 12 Min Max 52 60 Units MHz % ns ns ns ns ns
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Figure 83
- Receive ATM Cell Interface Timing
R F C LK tS R F C LK RENB R A D R [4:0] tP R F C LK RCA D R C A [4:1] tH R F C LK
R F C LK
RENB
tPR F C LK R D A T [15:0] R P R T Y[1 :0] RSOC RCA tZ B R F C LK
tZR F C LK
V a lid D a ta
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Table 48 Symbol fTICLK
- Transmit Interface Timing (Figure 84) Description TICLK[x] Frequency: DS3 Framer (TFRM[1:0] = 00) E3 Framer (TFRM[1:0] = 01) J2 Framer (TFRM[1:0] = 10) framer bypass (TFRM[1:0] = 11) 52 35 7 52 MHz Min Typ Max Units
t0TICLK
TICLK[x] minimum pulse width low: DS3 Framer (TFRM[1:0] = 00) E3 Framer (TFRM[1:0] = 01) J2 Framer (TFRM[1:0] = 10) framer bypass (TFRM[1:0] = 11) 7.7 11 57 7.7 ns
t1TICLK
TICLK[x] minimum pulse width high: DS3 Framer (TFRM[1:0] = 00) E3 Framer (TFRM[1:0] = 01) J2 Framer (TFRM[1:0] = 10) framer bypass (TFRM[1:0] = 11) 7.7 11 57 7.7 5 1 5 1 5 1 5 ns ns ns ns ns ns ns ns
tSTIOHM tHTIOHM tSTDATI tHTDATI tSLTIOHM tHLTIOHM tSLTDATI
TIOHM/TFPI/TMFPI[x] to TICLK[x] Set-up Time TIOHM/TFPI/TMFPI[x] to TICLK[x] Hold Time TDATI[x] to TICLK[x] Set-up Time TDATI[x] to TICLK[x] Hold Time TIOHM/TFPI/TMFPI[x] to RCLK[x] Set-up Time (LOOPT=1) TIOHM/TFPI/TMFPI[x] to RCLK[x] Hold Time (LOOPT=1) TDATI[x] to RCLK[x] Set-up Time (LOOPT=1)
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Symbol tHLTDATI tPTFPO
Description TDATI[x] to RCLK[x] Hold Time (LOOPT=1) TICLK[x] to TFPO/TMFPO[x] Prop Delay, or RCLK[x] to TFPO/TMFPO[x] Prop Delay when loop timing is used. TDATI[x] to TGAPCLK[x] Set-up Time TDATI[x] to TGAPCLK[x] Hold Time REF8KI pulse width4 TOH[x] to TOHCLK[x] Set-Up Time TOH[x] to TOHCLK[x] Hold Time TOHINS[x] to TOHCLK[x] Set-Up Time TOHINS[x] to TOHCLK[x] Hold Time TOHCLK[x] to TOHFP[x] Prop Delay TPOH[x] to TPOHCLK[x] Set-Up Time TPOH[x] to TPOHCLK[x] Hold Time TPOHINS[x] to TPOHCLK[x] Set-Up Time TPOHINS[x] to TPOHCLK[x] Hold Time TPOHCLK[x] to TPOHFP[x] Prop Delay TCLK[x] Edge to TPOS/TDATO[x] Prop Delay TCLK[x] Edge to TNEG/TOHM[x] Prop Delay TICLK[x] High to TPOS/TDATO[x] Prop Delay
Min 1 2
Typ
Max
Units ns
16
ns
tSTGAP tHTGAP tWREF8KI tSTOH tHTOH tSTOHINS tHTOHINS tPTOHFP tSTPOH tHTPOH tSTPOHIN tHTPOHIN tPTPOHFP tPTPOS tPTNEG tPTPOS2
3 2 15 20 20 20 20 -15 20 20 20 20 -15 -1 -1 2 20 4.5 4.5 13 20
ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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Symbol tPTNEG2 Figure 84
Description TICLK[x] High to TNEG/TOHM[x] Prop Delay - Transmit Interface Timing
Min 2
Typ
Max 13
Units ns
T IC LK [x]/R C LK [x] tS LT IO H M tS T IO H M T IO H M /T FP I/T M FP I[x] tH LT IO H M tH T IO H M
T IC LK [x]/R C LK [x] tS LT D AT I tS T DAT I T D A T I[x] tH LT D AT I tH T DAT I
T IC LK [x] / R C LK [x]
tPT FPO T FP O/T M FP O[x]
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T G A P C LK [x] tS T G A P T D A T I[x] tH T G A P
tW R E F8K I R E F 8K I
T O H C LK [x]
tS T O H T O H [x] tS T O H IN S
tH T O H
tH T O H IN S
T O H IN S [x]
T O H C LK [x]
tP T O HF P T O H FP [x]
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T P O H C LK [x] tS T P O H T P O H[x] tS T PO HIN T P O H IN S [x] tH T PO HIN tH T P O H
T P O H C LK [x]
tPT P O H FP T P O H FP [x]
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TIC LK = 0, TC LK IN V= 0
TIC LK = 0, TC LK IN V= 1
T ICLK[x]
T ICL K[x]
T CLK[x]
T CLK[x]
tPTP O S
tPTP O S
T PO S /T D AT O [x]
T PO S /T D AT O [x]
tPTN E G
T NE G /T O H M [x] T NE G /T O H M [x]
tPTN E G
TIC LK = 1, TC L K IN V = X
T ICL K[x]
T CL K[x]
tPTP O S 2
T PO S /T D AT O [x]
tPTN E G 2
T NE G /T O H M [x]
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Table 49 Symbol fRCLK
- Receive Interface Timing (Figure 85) Description RCLK[x] Frequency: DS3 Framer (RFRM[1:0] = 00) E3 Framer (RFRM[1:0] = 01) J2 Framer (RFRM[1:0] = 10) framer bypass (RFRM[1:0] = 11) 52 35 7 52 MHz MHz Min Max Units
t0RCLK
RCLK[x] minimum pulse width low: DS3 Framer (RFRM[1:0] = 00) E3 Framer (RFRM[1:0] = 01) J2 Framer (RFRM[1:0] = 10) framer bypass (RFRM[1:0] = 11) 7.7 11 57 7.7 ns
t1RCLK
RCLK[x] minimum pulse width high: DS3 Framer (RFRM[1:0] = 00) E3 Framer (RFRM[1:0] = 01) J2 Framer (RFRM[1:0] = 10) framer bypass (RFRM[1:0] = 11) 7.7 11 57 7.7 4 1 4 1 2 1 1 -2 13 13 13 10 ns ns ns ns ns ns ns ns ns
tSRPOS tHRPOS tSRNEG tHRNEG tPRRDATO tPRRFPO tPRROVRHD tPFRDATO
RPOS/RDATI Set-up Time RPOS/RDATI Hold Time RNEG/ROHM Set-Up Time RNEG/ROHM Hold Time RSCLK[x]/RGAPCLK[x] rising edge to RDATO[x] Prop Delay RSCLK[x] rising edge to RFPO/RMFPO[x] Prop Delay RSCLK[x] rising edge to ROVRHD[x] Prop Delay RSCLK[x]/RGAPCLK[x] falling edge to RDATO[x] Prop Delay
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Symbol tPFRFPO tPFROVRHD tPROH tPROHFP tPRPOH tPRPOHFP Figure 85
Description RSCLK[x] falling edge to RFPO/RMFPO[x] Prop Delay RSCLK[x] falling edge to ROVRHD[x] Prop Delay
Min -2 -2
Max 10 10 20 20 20 20
Units ns ns ns ns ns ns
ROHCLK[x] Low to ROH[x] Prop Delay -15 ROHCLK[x] Low to ROHFP[x] Prop Delay RPOHCLK[x] Low to RPOH[x] Prop Delay RPOHCLK[x] Low to RPOHFP[x] Prop Delay - Receive Interface Timing -15 -15 -15
R C LK [x] tS RP O S R P O S /R D A T I[x] tS RN E G R N E G /R O H M [x] tH RN E G tH RP O S
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R S CLK /RG AP C LK[x]
tP FR D AT O R D AT O [x]
tP R R D A T O
tP FR F PO R FP O /R M FP O [x]
tP RR FP O
tPFR O V RH D R O V R HD [x]
tPRR O V RH D
R O H C LK [x]
tP R O H R O H [x]
tP R O H F P R O H FP [x]
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R P O H C LK [x]
tP R P O H R P O H [x]
tP R P O H FP R P O H FP [x]
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Table 50 Symbol t1TCK t0TCK tSTMS, tSTDI THTMS, THTDI TPTDO TVTRSTB
- JTAG Port Interface (Figure 86) Description TCK high pulse width5 TCK low pulse width5 TMS and TDI Set-up time to TCK1 100 50 Min Typical Max Units ns ns ns
TMS and TDI Hold time to TCK2
50
ns
TCK Low to TDO Valid6,7 TRSTB minimum pulse width4,5
2 100
50
ns ns
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Figure 86
- JTAG Port Interface Timing
TCK
t0 T C K
t1 T C K
tS T M S TMS
tH T M S
tS T DI TDI
tH T DI
TCK
tP T D O TDO
tVT RS T B TRSTB
Notes on Input Timing: 1. When a set-up time is specified between an input and a clock, the set-up time is the time in nanoseconds from the 1.4 Volt point of the input to the 1.4 Volt point of the clock.
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2. When a hold time is specified between an input and a clock, the hold time is the time in nanoseconds from the 1.4 Volt point of the clock to the 1.4 Volt point of the input. 3. It is recommended that the load on TGAPCLK[x] be kept less than 50pF. A larger load on these pins may result in functional failures. 4. This parameter is guaranteed by design. No production tests are done on this parameter. 5. High pulse width is measured from the 1.4 Volt points of the rise and fall ramps. Low pulse width is measured from the 1.4 Volt points of the fall and rise ramps. Notes on Output Timing: 6. Output propagation delay time is the time in nanoseconds from the 1.4 Volt point of the reference signal to the 1.4 Volt point of the output. 7. Maximum and minimum output propagation delays are measured with a 50 pF load on the outputs.
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18
ORDERING AND THERMAL INFORMATION Table 51 PART NO PM7346 Table 52 PART NO. PM7346 - Packaging Information DESCRIPTION 256-pin Ball Grid Array (SBGA) - Thermal Information CASE TEMPERATURE -40C to 85C Theta Ja 19 C/W Theta Jc 5 C/W
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19
MECHANICAL INFORMATION
0.127
A
-A-
D1, M
1
A1 BALL CORNER
D
20 -B.30 A CAS BS
A1 BALL CORNER
19 6 18 16 14 12 10 8 4 2 5 31 7 17 15 13 11 9 A B C D E F G H J K L M N P R T U V W Y
A1 BALL I.D. INK MARK
b
E A
E1, N
e
0.127 A
TOP VIEW A BOTTOM VIEW
DIE SIDE
e
A
A2
bbb aaa
C
ccc -C-
P
A1
SIDE VIEW
SEATING PLANE
A-A SECTION VIEW
ddd
Notes: 1) ALL DIMENSIONS IN MILLIMETER. 2) DIMENSION aaa DENOTES COPLANARITY 3) DIMENSION bbb DENOTES PARALLEL 4) DIMENSION ccc DENOTES FLATNESS
PACKAGE TYPE: 256 PIN THERMAL BALL GRID ARRAY BODY SIZE: 27 x 27 x 1.45 MM Dim. Min. Nom. Max. A 1.32 1.45 1.58 A1 0.56 0.63 0.70 A2 0.76 0.82 0.88 D 26.90 27.00 27.10 D1 24.03 24.13 24.23 E 26.90 27.00 27.10 E1 24.03 24.13 24.23 20x20 1.27 M,N e b 0.60 0.75 0.90 0.15 0.15 0.20 aaa bbb ccc ddd 0.15 0.33 0.50 P 0.20 0.30 0.35
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, BC Canada V5A 4V7 Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com
Document Information: Corporate Information: Application Information:
None of the information contained in this document constitutes an express or implied warranty by PMC-Sierra, Inc. as to the sufficiency, fitness or suitability for a particular purpose of any such information or the fitness, or suitability for a particular purpose, merchantability, performance, compatibility with other parts or systems, of any of the products of PMC-Sierra, Inc., or any portion thereof, referred to in this document. PMC-Sierra, Inc. expressly disclaims all representations and warranties of any kind regarding the contents or use of the information, including, but not limited to, express and implied warranties of accuracy, completeness, merchantability, fitness for a particular use, or non-infringement. In no event will PMC-Sierra, Inc. be liable for any direct, indirect, special, incidental or consequential damages, including, but not limited to, lost profits, lost business or lost data resulting from any use of or reliance upon the information, whether or not PMC-Sierra, Inc. has been advised of the possibility of such damage. (c) 1999 PMC-Sierra, Inc. PMC-960835 (R6) ref PMC960486 (R6) Issue date: May 1999
PROPRIETARY AND CONFIDENTIAL TO PMC-SIERRA, INC., AND FOR ITS CUSTOMERS' INTERNAL USE

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